Fix detecting missing reg types, bug1570.

Changes

@@ -24,6 +24,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Support quoted arguments in -f files, bug1535. [Yves Mathieu]
 
+****  Fix detecting missing reg types, bug1570. [Jacko Dirks]
+
 ****  Fix multithreaded yield behavior when no work.  [Patrick Stewart]
 
 ****  Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563,

src/V3Ast.h

@@ -601,7 +601,6 @@ public:
     bool isProcAssignable() const {
         return (m_e==GPARAM || m_e==LPARAM || m_e==GENVAR
                 || m_e==VAR
-                || m_e==TRIWIRE || m_e==TRI0 || m_e==TRI1 || m_e==PORT
                 || m_e==BLOCKTEMP || m_e==MODULETEMP || m_e==STMTTEMP
                 || m_e==XTEMP || m_e==IFACEREF);
     }

src/V3Undriven.cpp

@@ -331,7 +331,9 @@ private:
         // Any variable
         if (nodep->lvalue()
             && !VN_IS(nodep, VarXRef)) {  // Ignore interface variables and similar ugly items
-            if (m_inProcAssign && !nodep->varp()->varType().isProcAssignable()) {
+            if (m_inProcAssign && !nodep->varp()->varType().isProcAssignable()
+                && !nodep->varp()->isDeclTyped()
+                && !nodep->varp()->isFuncLocal()) {
                 nodep->v3warn(PROCASSWIRE, "Procedural assignment to wire, perhaps intended var"
                               " (IEEE 2017 6.5): "
                               +nodep->prettyNameQ());

src/verilog.y

@@ -121,12 +121,7 @@ public:
 	    fl->v3warn(ENDLABEL,"End label '"<<*endnamep<<"' does not match begin label '"<<name<<"'");
 	}
     }
-    void setVarDecl(AstVarType type) {
+    void setVarDecl(AstVarType type) { m_varDecl = type; }
-        m_varDecl = type;
-        if (type != AstVarType::UNKNOWN && type != AstVarType::PORT) {
-            m_varDeclTyped = true;
-        }
-    }
     void setDType(AstNodeDType* dtypep) {
 	if (m_varDTypep) { m_varDTypep->deleteTree(); m_varDTypep=NULL; } // It was cloned, so this is safe.
 	m_varDTypep = dtypep;
@@ -1306,7 +1301,7 @@ net_declaration<nodep>:		// IEEE: net_declaration - excluding implict
 	;
 
 net_declarationFront:		// IEEE: beginning of net_declaration
-		net_declRESET net_type   strengthSpecE net_scalaredE net_dataTypeE { VARDTYPE($5); }
+		net_declRESET net_type   strengthSpecE net_scalaredE net_dataTypeE { VARDTYPE_NDECL($5); }
 	//UNSUP	net_declRESET yINTERCONNECT signingE rangeListE { VARNET($2); VARDTYPE(x); }
 	;
 

test_regress/t/t_cdc_async_bad.v

@@ -67,7 +67,7 @@ module Flop (
              input clk,
              input d,
              input rst_n,
-             output q);
+             output logic q);
 
    always @ (posedge clk or negedge rst_n) begin
       if (!rst_n) q <= 1'b0;

test_regress/t/t_clocker.v

@@ -16,9 +16,9 @@ module t (/*AUTOARG*/
    res16
    );
    input clk;
-   output        res;
+   output reg        res;
-   output [7:0]  res8;
+   output reg [7:0]  res8;
-   output [15:0] res16;
+   output reg [15:0] res16;
 
 
    wire [7:0] clkSet;

test_regress/t/t_dedupe_clk_gate.v

@@ -19,7 +19,7 @@ endmodule
 
 module flop_gated_latch(q,d,clk,en);
   input d, clk, en;
-  output q;
+  output reg q;
   wire gated_clock;
   clock_gate_latch clock_gate(gated_clock, clk, en);
   always @(posedge gated_clock) begin
@@ -29,7 +29,7 @@ endmodule
 
 module flop_gated_flop(q,d,clk,en);
   input d, clk, en;
-  output q;
+  output reg q;
   wire gated_clock;
   clock_gate_flop clock_gate(gated_clock, clk, en);
   always @(posedge gated_clock) begin

test_regress/t/t_dedupe_seq_logic.v

@@ -105,7 +105,7 @@ module rlr(sum,a,b,c,d,clk);
 endmodule
 
 module add(sum,x,y,clk);
-  output sum;
+  output reg sum;
   input x,y,clk;
   reg t1,t2;
   always @(posedge clk) begin
@@ -114,7 +114,7 @@ module add(sum,x,y,clk);
 endmodule
 
 module add2(sum,x,y,clk);
-  output sum;
+  output reg sum;
   input x,y,clk;
   reg t1,t2;
   always @(posedge clk) begin

test_regress/t/t_embed1_child.v

@@ -14,9 +14,9 @@ module t_embed1_child (/*AUTOARG*/
    input  bit_in;
    output bit_out;
    input  [30:0] vec_in;
-   output [30:0] vec_out;
+   output logic [30:0] vec_out;
    input  [123:0] wide_in;
-   output [123:0] wide_out;
+   output logic [123:0] wide_out;
    output 	  did_init_out;
 
    input 	  is_ref;

test_regress/t/t_embed1_wrap.v

@@ -12,10 +12,10 @@ module t_embed1_wrap (/*AUTOARG*/
 
    /*AUTOINOUTMODULE("t_embed1_child")*/
    // Beginning of automatic in/out/inouts (from specific module)
-   output		bit_out;
+   output bit           bit_out;
-   output [30:0]	vec_out;
+   output bit [30:0]    vec_out;
-   output [123:0]	wide_out;
+   output bit [123:0]   wide_out;
-   output		did_init_out;
+   output bit           did_init_out;
    input		clk;
    input		bit_in;
    input [30:0] 	vec_in;

test_regress/t/t_emit_memb_limit.pl

@@ -16,10 +16,10 @@ sub gen {
 
     my $fh = IO::File->new(">$filename");
     $fh->print("// Generated by t_emit_memb_limit.pl\n");
-    $fh->print("module t (i,clk,o);\n");
+    $fh->print("module t (i, clk, o);\n");
     $fh->print("  input clk;\n");
     $fh->print("  input i;\n");
-    $fh->print("  output o;\n");
+    $fh->print("  output logic o;\n");
     for (my $i=0; $i<($n+1); ++$i) {
         $fh->print("  logic r$i;\n");
     }

test_regress/t/t_extend_class.v

@@ -38,7 +38,7 @@ module t_extend_class_v (/*AUTOARG*/
    );
 
    input [31:0]  in;
-   output [31:0] out;
+   output logic [31:0] out;
 
    always @* begin
       // When "in" changes, call my method

test_regress/t/t_func_unit.v

@@ -3,15 +3,15 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2019 by Wilson Snyder.
 
-task tsk(output fo);
+task tsk(output tfo);
-   assign fo = 1'b0;
+   tfo = 1'b0;
 endtask
 
 module t (/*AUTOARG*/
    // Outputs
    to
    );
-   output to[2:0];
+   output reg to[2:0];
 
    integer i = 0;
 

test_regress/t/t_mem_slot.v

@@ -12,7 +12,7 @@ module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal);
    input        BitToChange;
    input        BitVal;
    input  [1:0] SlotToReturn;
-   output [1:0] OutputVal;
+   output reg [1:0] OutputVal;
 
    reg    [1:0] Array[2:0];
 

test_regress/t/t_order_multidriven.v

@@ -162,13 +162,13 @@ module FooMemImpl(
     input                   a_wen,
     input   [7:0]           a_addr,
     input   [7:0]           a_wdata,
-    output  [7:0]           a_rdata,
+    output reg [7:0]        a_rdata,
 
     input                   b_clk,
     input                   b_wen,
     input   [7:0]           b_addr,
     input   [7:0]           b_wdata,
-    output  [7:0]           b_rdata
+    output reg [7:0]        b_rdata
     );
 
     /* verilator lint_off MULTIDRIVEN */

test_regress/t/t_struct_anon.v

@@ -15,8 +15,8 @@ struct packed {
 } struct2;
 
 module t (
-    output [63:0] 	s1,
+    output logic [63:0] s1,
-    output [63:0] 	s2
+    output logic [63:0] s2
 );
    initial struct1 = 64'h123456789_abcdef0;
    always_comb s1 = struct1;

test_regress/t/t_var_dup_bad.out

@@ -47,6 +47,7 @@
    output bad_reout_port
           ^~~~~~~~~~~~~~
 %Error: t/t_var_dup_bad.v:72: Duplicate declaration of signal: 'bad_rewire'
+                            : ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)
    wire bad_rewire;
         ^~~~~~~~~~
         t/t_var_dup_bad.v:69: ... Location of original declaration

test_regress/t/t_var_pinsizes.v

@@ -26,22 +26,22 @@ module t (/*AUTOARG*/
    input 	 i1a2 [1:0];
    input [93:0]  i94a3 [2:0];
 
-   output 	  o1;
+   output logic 	  o1;
-   output [7:0]   o8;
+   output logic [7:0]   o8;
-   output [15:0]  o16;
+   output logic [15:0]  o16;
-   output [31:0]  o32;
+   output logic [31:0]  o32;
-   output [63:0]  o64;
+   output logic [63:0]  o64;
-   output [64:0]  o65;
+   output logic [64:0]  o65;
-   output [127:0] o128;
+   output logic [127:0] o128;
-   output [512:0] o513;
+   output logic [512:0] o513;
-   output	  o1a2 [1:0];
+   output logic 	  o1a2 [1:0];
-   output [93:0]  o94a3 [2:0];
+   output logic [93:0]  o94a3 [2:0];
 
    input [0:0] 	 ibv1 /*verilator sc_bv*/;
    input [15:0]  ibv16 /*verilator sc_bv*/;
 
-   output [0:0]   obv1 /*verilator sc_bv*/;
+   output logic [0:0]   obv1 /*verilator sc_bv*/;
-   output [15:0]  obv16 /*verilator sc_bv*/;
+   output logic [15:0]  obv16 /*verilator sc_bv*/;
 
    always @ (posedge clk) begin
       o1 <= i1;

test_regress/t/t_wire_beh1364_bad.out

@@ -0,0 +1,13 @@
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+                                             : ... In instance t
+      w = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+                                             : ... In instance t
+      o = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+                                             : ... In instance t
+      oa = '0;   
+      ^~
+%Error: Exiting due to

test_regress/t/t_wire_beh1364_bad.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   o, oa, ro, roa
+   );
+
+   wire w;
+   reg  r;
+   output o;
+   output [1:0] oa;
+   output reg ro;
+   output reg [1:0] roa;
+   //1800 only:
+   //output var vo;
+   //output var [1:0] voa;
+
+   initial begin
+      w = '0;  // Error
+      o = '0;  // Error
+      oa = '0;  // Error
+      r = '0;  // Not an error
+      ro = '0;  // Not an error
+      roa = '0;  // Not an error
+      //vo = '0;  // Not an error
+      //voa = '0;  // Not an error
+   end
+
+endmodule

test_regress/t/t_wire_beh1800_bad.out

@@ -0,0 +1,13 @@
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+                                             : ... In instance t
+      w = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+                                             : ... In instance t
+      o = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+                                             : ... In instance t
+      oa = '0;   
+      ^~
+%Error: Exiting due to

test_regress/t/t_wire_beh1800_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only --language 1800-2017"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_wire_beh1800_bad.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   o, oa, ro, roa, vo, voa
+   );
+
+   wire w;
+   reg  r;
+   output o;
+   output [1:0] oa;
+   output reg ro;
+   output reg [1:0] roa;
+   // 1800 only
+   output var vo;
+   output var [1:0] voa;
+
+   initial begin
+      w = '0;  // Error
+      o = '0;  // Error
+      oa = '0;  // Error
+      r = '0;  // Not an error
+      ro = '0;  // Not an error
+      roa = '0;  // Not an error
+      vo = '0;  // Not an error
+      voa = '0;  // Not an error
+   end
+
+endmodule

test_regress/t/t_wire_beh_bad.out

@@ -1,9 +0,0 @@
-%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): 'r'
-                                        : ... In instance t
-   assign r = 1'b1;
-          ^
-%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
-                                         : ... In instance t
-   always @ (r) w = 1'b0;
-                ^
-%Error: Exiting due to

test_regress/t/t_wire_beh_bad.v

@@ -1,14 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2018 by Wilson Snyder.
-
-module t (/*AUTOARG*/);
-
-   wire w;
-   reg  r;
-
-   assign r = 1'b1;
-   always @ (r) w = 1'b0;
-
-endmodule

test_regress/t/t_wire_behp1364_bad.out

@@ -0,0 +1,13 @@
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+                                              : ... In instance t
+      w = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+                                              : ... In instance t
+      o = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+                                              : ... In instance t
+      oa = '0;   
+      ^~
+%Error: Exiting due to

test_regress/t/t_wire_behp1364_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only --language 1364-2001"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_wire_behp1364_bad.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+module t (
+   output o,
+   output [1:0] oa,
+   output reg ro,
+   output reg [1:0] roa
+   //1800 only:
+   //output var vo;
+   //output var [1:0] voa;
+   );
+
+   wire w;
+   reg  r;
+
+   initial begin
+      w = '0;  // Error
+      o = '0;  // Error
+      oa = '0;  // Error
+      r = '0;  // Not an error
+      ro = '0;  // Not an error
+      roa = '0;  // Not an error
+      //vo = '0;  // Not an error
+      //voa = '0;  // Not an error
+   end
+
+endmodule

test_regress/t/t_wire_behp1800_bad.out

@@ -0,0 +1,13 @@
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:20: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
+                                              : ... In instance t
+      w = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:21: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'o'
+                                              : ... In instance t
+      o = '0;   
+      ^
+%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'oa'
+                                              : ... In instance t
+      oa = '0;   
+      ^~
+%Error: Exiting due to

test_regress/t/t_wire_behp1800_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only --language 1800-2017"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_wire_behp1800_bad.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+module t (
+   output o,
+   output [1:0] oa,
+   output reg ro,
+   output reg [1:0] roa,
+   // 1800 only
+   output var vo,
+   output var [1:0] voa
+   );
+
+   wire w;
+   reg  r;
+
+   initial begin
+      w = '0;  // Error
+      o = '0;  // Error
+      oa = '0;  // Error
+      r = '0;  // Not an error
+      ro = '0;  // Not an error
+      roa = '0;  // Not an error
+      vo = '0;  // Not an error
+      voa = '0;  // Not an error
+   end
+
+endmodule