Merge branch 'master' into develop-v5
This commit is contained in:
Geza Lore
commit
2ad0bcbba9
|
|
@ -14,7 +14,7 @@ AC_INIT([Verilator],[5.001 devel],
|
||||||
# and commit using "devel release" or "Version bump" message
|
# and commit using "devel release" or "Version bump" message
|
||||||
# Then 'make maintainer-dist'
|
# Then 'make maintainer-dist'
|
||||||
|
|
||||||
AC_CONFIG_HEADER(src/config_build.h)
|
AC_CONFIG_HEADERS(src/config_build.h)
|
||||||
AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)
|
AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)
|
||||||
|
|
||||||
# Version
|
# Version
|
||||||
|
|
|
||||||
|
|
@ -41,21 +41,21 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc<=cyc+1;
|
cyc<=cyc+1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
a <= 32'hfeed0000;
|
a <= 32'hfeed0000;
|
||||||
b <= 32'h0000face;
|
b <= 32'h0000face;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
if (c != 32'hfeedface) $stop;
|
if (c != 32'hfeedface) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
if (h != 32'hfeedface) $stop;
|
if (h != 32'hfeedface) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==7) begin
|
if (cyc==7) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -31,34 +31,34 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
|
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
|
||||||
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
|
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
|
||||||
if (posedge_wr_clocks) begin
|
if (posedge_wr_clocks) begin
|
||||||
//$write("[%0t] Wrclk\n", $time);
|
//$write("[%0t] Wrclk\n", $time);
|
||||||
m_dout <= m_din;
|
m_dout <= m_din;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc<=cyc+1;
|
cyc<=cyc+1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
$write(" %x\n",comb_pos_1);
|
$write(" %x\n",comb_pos_1);
|
||||||
m_din <= 32'hfeed;
|
m_din <= 32'hfeed;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
$write(" %x\n",comb_pos_1);
|
$write(" %x\n",comb_pos_1);
|
||||||
m_din <= 32'he11e;
|
m_din <= 32'he11e;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
m_din <= 32'he22e;
|
m_din <= 32'he22e;
|
||||||
$write(" %x\n",comb_pos_1);
|
$write(" %x\n",comb_pos_1);
|
||||||
if (m_dout!=32'hfeed) $stop;
|
if (m_dout!=32'hfeed) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
if (m_dout!=32'he11e) $stop;
|
if (m_dout!=32'he11e) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -59,35 +59,35 @@ module t (/*AUTOARG*/
|
||||||
// (The checker block is an exception, it won't split.)
|
// (The checker block is an exception, it won't split.)
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc<=cyc+1;
|
cyc<=cyc+1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
m_din <= 16'hfeed;
|
m_din <= 16'hfeed;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
m_din <= 16'he11e;
|
m_din <= 16'he11e;
|
||||||
//$write(" A %x %x\n", a_split_1, a_split_2);
|
//$write(" A %x %x\n", a_split_1, a_split_2);
|
||||||
if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop;
|
if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop;
|
||||||
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
||||||
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
|
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==5) begin
|
if (cyc==5) begin
|
||||||
m_din <= 16'he22e;
|
m_din <= 16'he22e;
|
||||||
if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop;
|
if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop;
|
||||||
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
||||||
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
|
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==6) begin
|
if (cyc==6) begin
|
||||||
m_din <= 16'he33e;
|
m_din <= 16'he33e;
|
||||||
if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop;
|
if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop;
|
||||||
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
|
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
|
||||||
if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop;
|
if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==7) begin
|
if (cyc==7) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end // always @ (posedge clk)
|
end // always @ (posedge clk)
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -18,27 +18,27 @@ module t (/*AUTOARG*/
|
||||||
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
|
reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
/*AUTORESET*/
|
/*AUTORESET*/
|
||||||
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
||||||
c_split_1 <= 16'h0;
|
c_split_1 <= 16'h0;
|
||||||
c_split_2 <= 16'h0;
|
c_split_2 <= 16'h0;
|
||||||
c_split_3 <= 16'h0;
|
c_split_3 <= 16'h0;
|
||||||
c_split_4 <= 0;
|
c_split_4 <= 0;
|
||||||
c_split_5 <= 0;
|
c_split_5 <= 0;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
c_split_1 <= m_din;
|
c_split_1 <= m_din;
|
||||||
c_split_2 <= c_split_1;
|
c_split_2 <= c_split_1;
|
||||||
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
|
c_split_3 <= c_split_2 & {16{(cyc!=0)}};
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
c_split_4 <= 16'h4;
|
c_split_4 <= 16'h4;
|
||||||
c_split_5 <= 16'h5;
|
c_split_5 <= 16'h5;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
c_split_4 <= c_split_3;
|
c_split_4 <= c_split_3;
|
||||||
c_split_5 <= c_split_4;
|
c_split_5 <= c_split_4;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -46,29 +46,29 @@ module t (/*AUTOARG*/
|
||||||
reg [15:0] d_split_1, d_split_2;
|
reg [15:0] d_split_1, d_split_2;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
/*AUTORESET*/
|
/*AUTORESET*/
|
||||||
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
||||||
d_split_1 <= 16'h0;
|
d_split_1 <= 16'h0;
|
||||||
d_split_2 <= 16'h0;
|
d_split_2 <= 16'h0;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
d_split_1 <= m_din;
|
d_split_1 <= m_din;
|
||||||
d_split_2 <= d_split_1;
|
d_split_2 <= d_split_1;
|
||||||
d_split_1 <= ~m_din;
|
d_split_1 <= ~m_din;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// Not OK
|
// Not OK
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
/*AUTORESET*/
|
/*AUTORESET*/
|
||||||
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
||||||
// End of automatics
|
// End of automatics
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
$write(" foo %x", m_din);
|
$write(" foo %x", m_din);
|
||||||
$write(" bar %x\n", m_din);
|
$write(" bar %x\n", m_din);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -76,15 +76,15 @@ module t (/*AUTOARG*/
|
||||||
reg [15:0] e_split_1, e_split_2;
|
reg [15:0] e_split_1, e_split_2;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
/*AUTORESET*/
|
/*AUTORESET*/
|
||||||
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
||||||
e_split_1 = 16'h0;
|
e_split_1 = 16'h0;
|
||||||
e_split_2 = 16'h0;
|
e_split_2 = 16'h0;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
e_split_1 = m_din;
|
e_split_1 = m_din;
|
||||||
e_split_2 = e_split_1;
|
e_split_2 = e_split_1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -92,61 +92,61 @@ module t (/*AUTOARG*/
|
||||||
reg [15:0] f_split_1, f_split_2;
|
reg [15:0] f_split_1, f_split_2;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
/*AUTORESET*/
|
/*AUTORESET*/
|
||||||
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
||||||
f_split_1 = 16'h0;
|
f_split_1 = 16'h0;
|
||||||
f_split_2 = 16'h0;
|
f_split_2 = 16'h0;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
f_split_2 = f_split_1;
|
f_split_2 = f_split_1;
|
||||||
f_split_1 = m_din;
|
f_split_1 = m_din;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
|
//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
|
||||||
cyc<=cyc+1;
|
cyc<=cyc+1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
m_din <= 16'hfeed;
|
m_din <= 16'hfeed;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
m_din <= 16'he11e;
|
m_din <= 16'he11e;
|
||||||
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
||||||
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
|
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
|
||||||
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
|
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==5) begin
|
if (cyc==5) begin
|
||||||
m_din <= 16'he22e;
|
m_din <= 16'he22e;
|
||||||
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
|
||||||
// Two valid orderings, as we don't know which posedge clk gets evaled first
|
// Two valid orderings, as we don't know which posedge clk gets evaled first
|
||||||
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
|
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
|
||||||
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
|
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==6) begin
|
if (cyc==6) begin
|
||||||
m_din <= 16'he33e;
|
m_din <= 16'he33e;
|
||||||
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
|
if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
|
||||||
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
|
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
|
||||||
// Two valid orderings, as we don't know which posedge clk gets evaled first
|
// Two valid orderings, as we don't know which posedge clk gets evaled first
|
||||||
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
|
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
|
||||||
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
|
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==7) begin
|
if (cyc==7) begin
|
||||||
m_din <= 16'he44e;
|
m_din <= 16'he44e;
|
||||||
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
|
if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==8) begin
|
if (cyc==8) begin
|
||||||
m_din <= 16'he55e;
|
m_din <= 16'he55e;
|
||||||
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
|
if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
|
||||||
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
|
&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -83,8 +83,8 @@ module t (/*AUTOARG*/
|
||||||
$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
|
$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
|
||||||
`endif
|
`endif
|
||||||
if (cnt[30:4]==1) begin
|
if (cnt[30:4]==1) begin
|
||||||
// big endian
|
// big endian
|
||||||
if (slc==0) begin
|
if (slc==0) begin
|
||||||
// full array
|
// full array
|
||||||
`checkh($dimensions (array_bg), 3);
|
`checkh($dimensions (array_bg), 3);
|
||||||
`checkh($bits (array_bg), WA*WB*WC);
|
`checkh($bits (array_bg), WA*WB*WC);
|
||||||
|
|
@ -96,7 +96,7 @@ module t (/*AUTOARG*/
|
||||||
`checkh($increment (array_bg, dim), 1 );
|
`checkh($increment (array_bg, dim), 1 );
|
||||||
`checkh($size (array_bg, dim), wdt );
|
`checkh($size (array_bg, dim), wdt );
|
||||||
end
|
end
|
||||||
end else if (slc==1) begin
|
end else if (slc==1) begin
|
||||||
// single array element
|
// single array element
|
||||||
`checkh($dimensions (array_bg[2]), 2);
|
`checkh($dimensions (array_bg[2]), 2);
|
||||||
`checkh($bits (array_bg[2]), WB*WC);
|
`checkh($bits (array_bg[2]), WB*WC);
|
||||||
|
|
@ -109,7 +109,7 @@ module t (/*AUTOARG*/
|
||||||
`checkh($size (array_bg[2], dim-1), wdt );
|
`checkh($size (array_bg[2], dim-1), wdt );
|
||||||
end
|
end
|
||||||
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
|
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
|
||||||
end else if (slc==2) begin
|
end else if (slc==2) begin
|
||||||
// half array
|
// half array
|
||||||
`checkh($dimensions (array_bg[WA/2+1:2]), 3);
|
`checkh($dimensions (array_bg[WA/2+1:2]), 3);
|
||||||
`checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC);
|
`checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC);
|
||||||
|
|
@ -122,10 +122,10 @@ module t (/*AUTOARG*/
|
||||||
`checkh($size (array_bg[WA/2+1:2], dim), wdt);
|
`checkh($size (array_bg[WA/2+1:2], dim), wdt);
|
||||||
end
|
end
|
||||||
`endif
|
`endif
|
||||||
end
|
end
|
||||||
end else if (cnt[30:4]==2) begin
|
end else if (cnt[30:4]==2) begin
|
||||||
// little endian
|
// little endian
|
||||||
if (slc==0) begin
|
if (slc==0) begin
|
||||||
// full array
|
// full array
|
||||||
`checkh($dimensions (array_lt), 3);
|
`checkh($dimensions (array_lt), 3);
|
||||||
`checkh($bits (array_lt), WA*WB*WC);
|
`checkh($bits (array_lt), WA*WB*WC);
|
||||||
|
|
@ -137,7 +137,7 @@ module t (/*AUTOARG*/
|
||||||
`checkh($increment (array_lt, dim), -1 );
|
`checkh($increment (array_lt, dim), -1 );
|
||||||
`checkh($size (array_lt, dim), wdt );
|
`checkh($size (array_lt, dim), wdt );
|
||||||
end
|
end
|
||||||
end else if (slc==1) begin
|
end else if (slc==1) begin
|
||||||
// single array element
|
// single array element
|
||||||
`checkh($dimensions (array_lt[2]), 2);
|
`checkh($dimensions (array_lt[2]), 2);
|
||||||
`checkh($bits (array_lt[2]), WB*WC);
|
`checkh($bits (array_lt[2]), WB*WC);
|
||||||
|
|
@ -150,7 +150,7 @@ module t (/*AUTOARG*/
|
||||||
`checkh($size (array_lt[2], dim-1), wdt );
|
`checkh($size (array_lt[2], dim-1), wdt );
|
||||||
end
|
end
|
||||||
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
|
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
|
||||||
end else if (slc==2) begin
|
end else if (slc==2) begin
|
||||||
// half array
|
// half array
|
||||||
`checkh($dimensions (array_lt[2:WA/2+1]), 3);
|
`checkh($dimensions (array_lt[2:WA/2+1]), 3);
|
||||||
`checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC);
|
`checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC);
|
||||||
|
|
@ -163,7 +163,7 @@ module t (/*AUTOARG*/
|
||||||
`checkh($size (array_lt[2:WA/2+1], dim), wdt );
|
`checkh($size (array_lt[2:WA/2+1], dim), wdt );
|
||||||
end
|
end
|
||||||
`endif
|
`endif
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -20,8 +20,8 @@ module t (/*AUTOARG*/
|
||||||
reg c;
|
reg c;
|
||||||
|
|
||||||
array_test array_test_i (/*AUTOINST*/
|
array_test array_test_i (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk));
|
.clk (clk));
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -11,7 +11,7 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
// verilator lint_off LITENDIAN
|
// verilator lint_off LITENDIAN
|
||||||
logic arrd [0:1] = '{ 1'b1, 1'b0 };
|
logic arrd [0:1] = '{ 1'b1, 1'b0 };
|
||||||
// verilator lint_on LITENDIAN
|
// verilator lint_on LITENDIAN
|
||||||
|
|
@ -19,7 +19,7 @@ module t (/*AUTOARG*/
|
||||||
logic localbkw [1:0];
|
logic localbkw [1:0];
|
||||||
|
|
||||||
arr_rev arr_rev_u (
|
arr_rev arr_rev_u (
|
||||||
.arrbkw (arrd),
|
.arrbkw (arrd),
|
||||||
.y0(y0),
|
.y0(y0),
|
||||||
.y1(y1)
|
.y1(y1)
|
||||||
);
|
);
|
||||||
|
|
|
||||||
|
|
@ -11,13 +11,13 @@ module t (/*AUTOARG*/
|
||||||
inibble, onibble
|
inibble, onibble
|
||||||
);
|
);
|
||||||
|
|
||||||
input [3:0] inibble;
|
input [3:0] inibble;
|
||||||
input [106:0] onibble;
|
input [106:0] onibble;
|
||||||
|
|
||||||
output reg [3:0] nnext [0:7];
|
output reg [3:0] nnext [0:7];
|
||||||
|
|
||||||
// verilator lint_off WIDTH
|
// verilator lint_off WIDTH
|
||||||
wire [2:0] selline = (onibble >>> 102) & 7;
|
wire [2:0] selline = (onibble >>> 102) & 7;
|
||||||
// verilator lint_on WIDTH
|
// verilator lint_on WIDTH
|
||||||
|
|
||||||
always_comb begin
|
always_comb begin
|
||||||
|
|
|
||||||
|
|
@ -11,7 +11,7 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
reg toggle;
|
reg toggle;
|
||||||
|
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
wire [7:0] cyc_copy = cyc[7:0];
|
wire [7:0] cyc_copy = cyc[7:0];
|
||||||
|
|
@ -26,24 +26,24 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
toggle <= !cyc[0];
|
toggle <= !cyc[0];
|
||||||
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
|
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
`ifdef FAILING_ASSERTIONS
|
`ifdef FAILING_ASSERTIONS
|
||||||
assert (0) else $info;
|
assert (0) else $info;
|
||||||
assert (0) else $info("Info message");
|
assert (0) else $info("Info message");
|
||||||
assume (0) else $info("Info message from failing assumption");
|
assume (0) else $info("Info message from failing assumption");
|
||||||
assert (0) else $info("Info message, cyc=%d", cyc);
|
assert (0) else $info("Info message, cyc=%d", cyc);
|
||||||
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
|
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
|
||||||
InErrorBlock: assert (0) else $error("Error....");
|
InErrorBlock: assert (0) else $error("Error....");
|
||||||
assert (0) else $fatal(1,"Fatal....");
|
assert (0) else $fatal(1,"Fatal....");
|
||||||
`endif
|
`endif
|
||||||
end
|
end
|
||||||
if (cyc==10) begin
|
if (cyc==10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,28 +10,28 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
reg toggle;
|
reg toggle;
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle (toggle),
|
.toggle (toggle),
|
||||||
.cyc (cyc[31:0]));
|
.cyc (cyc[31:0]));
|
||||||
|
|
||||||
Sub sub1 (.*);
|
Sub sub1 (.*);
|
||||||
Sub sub2 (.*);
|
Sub sub2 (.*);
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
toggle <= !cyc[0];
|
toggle <= !cyc[0];
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
end
|
end
|
||||||
if (cyc==10) begin
|
if (cyc==10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -89,9 +89,9 @@ module Test
|
||||||
genvar i;
|
genvar i;
|
||||||
generate
|
generate
|
||||||
for (i=0; i<32; i=i+1)
|
for (i=0; i<32; i=i+1)
|
||||||
begin: cycval
|
begin: cycval
|
||||||
CycCover_i: `covclk( cyc[i] );
|
CycCover_i: `covclk( cyc[i] );
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
`ifndef verilator // Unsupported
|
`ifndef verilator // Unsupported
|
||||||
|
|
@ -99,8 +99,8 @@ module Test
|
||||||
// Using a more complicated property
|
// Using a more complicated property
|
||||||
property C1;
|
property C1;
|
||||||
@(posedge clk)
|
@(posedge clk)
|
||||||
disable iff (!toggle)
|
disable iff (!toggle)
|
||||||
cyc==5;
|
cyc==5;
|
||||||
endproperty
|
endproperty
|
||||||
cover property (C1) $display("*COVER: Cyc==5");
|
cover property (C1) $display("*COVER: Cyc==5");
|
||||||
|
|
||||||
|
|
@ -111,35 +111,35 @@ module Test
|
||||||
|
|
||||||
// Each bin value must be <= 32 bits. Strange.
|
// Each bin value must be <= 32 bits. Strange.
|
||||||
cyc_value : coverpoint cyc {
|
cyc_value : coverpoint cyc {
|
||||||
}
|
}
|
||||||
|
|
||||||
cyc_bined : coverpoint cyc {
|
cyc_bined : coverpoint cyc {
|
||||||
bins zero = {0};
|
bins zero = {0};
|
||||||
bins low = {1,5};
|
bins low = {1,5};
|
||||||
// Note 5 is also in the bin above. Only the first bin matching is counted.
|
// Note 5 is also in the bin above. Only the first bin matching is counted.
|
||||||
bins mid = {[5:$]};
|
bins mid = {[5:$]};
|
||||||
// illegal_bins // Has precidence over "first matching bin", creates assertion
|
// illegal_bins // Has precidence over "first matching bin", creates assertion
|
||||||
// ignore_bins // Not counted, and not part of total
|
// ignore_bins // Not counted, and not part of total
|
||||||
}
|
}
|
||||||
toggle : coverpoint (toggle) {
|
toggle : coverpoint (toggle) {
|
||||||
bins off = {0};
|
bins off = {0};
|
||||||
bins on = {1};
|
bins on = {1};
|
||||||
}
|
}
|
||||||
cyc5 : coverpoint (cyc==5) {
|
cyc5 : coverpoint (cyc==5) {
|
||||||
bins five = {1};
|
bins five = {1};
|
||||||
}
|
}
|
||||||
|
|
||||||
// option.at_least = {number}; // Default 1 - Hits to be considered covered
|
// option.at_least = {number}; // Default 1 - Hits to be considered covered
|
||||||
// option.auto_bin_max = {number}; // Default 64
|
// option.auto_bin_max = {number}; // Default 64
|
||||||
// option.comment = {string}
|
// option.comment = {string}
|
||||||
// option.goal = {number}; // Default 90%
|
// option.goal = {number}; // Default 90%
|
||||||
// option.name = {string}
|
// option.name = {string}
|
||||||
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
|
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
|
||||||
// option.weight = {number}; // Default 1
|
// option.weight = {number}; // Default 1
|
||||||
|
|
||||||
// CROSS
|
// CROSS
|
||||||
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
|
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
|
||||||
cross cyc_value, toggle;
|
cross cyc_value, toggle;
|
||||||
endgroup
|
endgroup
|
||||||
counter1 c1 = new();
|
counter1 c1 = new();
|
||||||
`endif
|
`endif
|
||||||
|
|
|
||||||
|
|
@ -13,8 +13,8 @@ module t (/*AUTOARG*/
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk));
|
.clk (clk));
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
|
|
|
||||||
|
|
@ -11,11 +11,11 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
reg a; initial a = 1'b1;
|
reg a; initial a = 1'b1;
|
||||||
reg b_fc; initial b_fc = 1'b0;
|
reg b_fc; initial b_fc = 1'b0;
|
||||||
reg b_pc; initial b_pc = 1'b0;
|
reg b_pc; initial b_pc = 1'b0;
|
||||||
reg b_oh; initial b_oh = 1'b0;
|
reg b_oh; initial b_oh = 1'b0;
|
||||||
reg b_oc; initial b_oc = 1'b0;
|
reg b_oc; initial b_oc = 1'b0;
|
||||||
wire a_l = ~a;
|
wire a_l = ~a;
|
||||||
wire b_oc_l = ~b_oc;
|
wire b_oc_l = ~b_oc;
|
||||||
|
|
||||||
|
|
@ -32,16 +32,16 @@ module t (/*AUTOARG*/
|
||||||
`else
|
`else
|
||||||
case ({a,b_fc})
|
case ({a,b_fc})
|
||||||
`endif
|
`endif
|
||||||
2'b0_0: ;
|
2'b0_0: ;
|
||||||
2'b0_1: ;
|
2'b0_1: ;
|
||||||
2'b1_0: ;
|
2'b1_0: ;
|
||||||
// Note no default
|
// Note no default
|
||||||
endcase
|
endcase
|
||||||
priority case ({a,b_fc})
|
priority case ({a,b_fc})
|
||||||
2'b0_0: ;
|
2'b0_0: ;
|
||||||
2'b0_1: ;
|
2'b0_1: ;
|
||||||
2'b1_0: ;
|
2'b1_0: ;
|
||||||
// Note no default
|
// Note no default
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -55,8 +55,8 @@ module t (/*AUTOARG*/
|
||||||
case (1'b1) // synopsys parallel_full
|
case (1'b1) // synopsys parallel_full
|
||||||
`endif
|
`endif
|
||||||
`endif
|
`endif
|
||||||
a: ;
|
a: ;
|
||||||
b_pc: ;
|
b_pc: ;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -68,46 +68,46 @@ module t (/*AUTOARG*/
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
a <= 1'b1;
|
a <= 1'b1;
|
||||||
b_fc <= 1'b0;
|
b_fc <= 1'b0;
|
||||||
b_pc <= 1'b0;
|
b_pc <= 1'b0;
|
||||||
b_oh <= 1'b0;
|
b_oh <= 1'b0;
|
||||||
b_oc <= 1'b0;
|
b_oc <= 1'b0;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
a <= 1'b0;
|
a <= 1'b0;
|
||||||
b_fc <= 1'b1;
|
b_fc <= 1'b1;
|
||||||
b_pc <= 1'b1;
|
b_pc <= 1'b1;
|
||||||
b_oh <= 1'b1;
|
b_oh <= 1'b1;
|
||||||
b_oc <= 1'b1;
|
b_oc <= 1'b1;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
a <= 1'b1;
|
a <= 1'b1;
|
||||||
b_fc <= 1'b0;
|
b_fc <= 1'b0;
|
||||||
b_pc <= 1'b0;
|
b_pc <= 1'b0;
|
||||||
b_oh <= 1'b0;
|
b_oh <= 1'b0;
|
||||||
b_oc <= 1'b0;
|
b_oc <= 1'b0;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
`ifdef FAILING_FULL
|
`ifdef FAILING_FULL
|
||||||
b_fc <= 1'b1;
|
b_fc <= 1'b1;
|
||||||
`endif
|
`endif
|
||||||
`ifdef FAILING_PARALLEL
|
`ifdef FAILING_PARALLEL
|
||||||
b_pc <= 1'b1;
|
b_pc <= 1'b1;
|
||||||
`endif
|
`endif
|
||||||
`ifdef FAILING_OH
|
`ifdef FAILING_OH
|
||||||
b_oh <= 1'b1;
|
b_oh <= 1'b1;
|
||||||
`endif
|
`endif
|
||||||
`ifdef FAILING_OC
|
`ifdef FAILING_OC
|
||||||
b_oc <= 1'b1;
|
b_oc <= 1'b1;
|
||||||
`endif
|
`endif
|
||||||
end
|
end
|
||||||
if (cyc==10) begin
|
if (cyc==10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -26,12 +26,12 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
// Not legal in some simulators, legal in others
|
// Not legal in some simulators, legal in others
|
||||||
// always @(* // cmt
|
// always @(* // cmt
|
||||||
// ) begin
|
// ) begin
|
||||||
// if (clk) begin end
|
// if (clk) begin end
|
||||||
// end
|
// end
|
||||||
|
|
||||||
always @ (*
|
always @ (*
|
||||||
) begin
|
) begin
|
||||||
if (clk) begin end
|
if (clk) begin end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -26,19 +26,19 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v
|
wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai;
|
reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai;
|
||||||
reg [`ADDR_WIDTH-1:0] addr;
|
reg [`ADDR_WIDTH-1:0] addr;
|
||||||
|
|
||||||
// Mux: takes in addr and datai and outputs datao
|
// Mux: takes in addr and datai and outputs datao
|
||||||
mux4096 mux4096 (/*AUTOINST*/
|
mux4096 mux4096 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.datao (datao[`DATA_WIDTH-1:0]),
|
.datao (datao[`DATA_WIDTH-1:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]),
|
.datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]),
|
||||||
.addr (addr[`ADDR_WIDTH-1:0]));
|
.addr (addr[`ADDR_WIDTH-1:0]));
|
||||||
|
|
||||||
|
|
||||||
// calculate what the answer should be from datai. This is bit
|
// calculate what the answer should be from datai. This is bit
|
||||||
|
|
@ -48,9 +48,9 @@ module t (/*AUTOARG*/
|
||||||
integer j;
|
integer j;
|
||||||
always @(datai or addr) begin
|
always @(datai or addr) begin
|
||||||
for(j=0;j<`DATA_WIDTH;j=j+1) begin
|
for(j=0;j<`DATA_WIDTH;j=j+1) begin
|
||||||
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
||||||
datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr);
|
datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr);
|
||||||
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -59,19 +59,19 @@ module t (/*AUTOARG*/
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
// initial the input data with random values
|
// initial the input data with random values
|
||||||
if (addr == 0) begin
|
if (addr == 0) begin
|
||||||
result = 1;
|
result = 1;
|
||||||
datai = 0;
|
datai = 0;
|
||||||
for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin
|
for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin
|
||||||
/* verilator lint_off WIDTH */
|
/* verilator lint_off WIDTH */
|
||||||
datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}});
|
datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}});
|
||||||
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
addr <= addr + 1;
|
addr <= addr + 1;
|
||||||
if (datao_check != datao) begin
|
if (datao_check != datao) begin
|
||||||
result = 0;
|
result = 0;
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end
|
||||||
|
|
||||||
`ifdef TEST_VERBOSE
|
`ifdef TEST_VERBOSE
|
||||||
|
|
@ -79,8 +79,8 @@ module t (/*AUTOARG*/
|
||||||
`endif
|
`endif
|
||||||
// only run the first 10 addresses for now
|
// only run the first 10 addresses for now
|
||||||
if (addr > 10) begin
|
if (addr > 10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -17,14 +17,14 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
ExampInst i
|
ExampInst i
|
||||||
(// Outputs
|
(// Outputs
|
||||||
.o (o[31:0]),
|
.o (o[31:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.i (1'b0)
|
.i (1'b0)
|
||||||
/*AUTOINST*/);
|
/*AUTOINST*/);
|
||||||
|
|
||||||
Prog p (/*AUTOINST*/
|
Prog p (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.si (si));
|
.si (si));
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (!a_finished) $stop;
|
if (!a_finished) $stop;
|
||||||
|
|
@ -37,7 +37,7 @@ endmodule
|
||||||
|
|
||||||
module InstModule (
|
module InstModule (
|
||||||
output logic [31:0] so,
|
output logic [31:0] so,
|
||||||
input si
|
input si
|
||||||
);
|
);
|
||||||
assign so = {32{si}};
|
assign so = {32{si}};
|
||||||
endmodule
|
endmodule
|
||||||
|
|
@ -52,9 +52,9 @@ module ExampInst (o,i);
|
||||||
|
|
||||||
InstModule instName
|
InstModule instName
|
||||||
(// Outputs
|
(// Outputs
|
||||||
.so (o[31:0]),
|
.so (o[31:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.si (i)
|
.si (i)
|
||||||
/*AUTOINST*/);
|
/*AUTOINST*/);
|
||||||
|
|
||||||
//bind InstModule Prog instProg
|
//bind InstModule Prog instProg
|
||||||
|
|
|
||||||
|
|
@ -14,8 +14,8 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
reg [7:0] p1;
|
reg [7:0] p1;
|
||||||
reg [7:0] p2;
|
reg [7:0] p2;
|
||||||
reg [7:0] p3;
|
reg [7:0] p3;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
p1 = 8'h01;
|
p1 = 8'h01;
|
||||||
|
|
@ -28,16 +28,16 @@ module t (/*AUTOARG*/
|
||||||
parameter int param3 = 8'h13;
|
parameter int param3 = 8'h13;
|
||||||
|
|
||||||
targetmod i_targetmod (/*AUTOINST*/
|
targetmod i_targetmod (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk));
|
.clk (clk));
|
||||||
|
|
||||||
//Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod
|
//Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod
|
||||||
//param1 not over-riden (as mycheck) (=> 0x31)
|
//param1 not over-riden (as mycheck) (=> 0x31)
|
||||||
//param2 explicitly bound to targetmod value (=> 0x22)
|
//param2 explicitly bound to targetmod value (=> 0x22)
|
||||||
//param3 explicitly bound to top value (=> 0x13)
|
//param3 explicitly bound to top value (=> 0x13)
|
||||||
//p1 implictly bound (.*), takes value from targetmod (=> 0x04)
|
//p1 implictly bound (.*), takes value from targetmod (=> 0x04)
|
||||||
//p2 explictly bound to targetmod (=> 0x05)
|
//p2 explictly bound to targetmod (=> 0x05)
|
||||||
//p3 explictly bound to top (=> 0x03)
|
//p3 explictly bound to top (=> 0x03)
|
||||||
|
|
||||||
// Alternative unsupported form is i_targetmod
|
// Alternative unsupported form is i_targetmod
|
||||||
bind targetmod mycheck
|
bind targetmod mycheck
|
||||||
|
|
@ -50,7 +50,7 @@ module t (/*AUTOARG*/
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module targetmod (input clk);
|
module targetmod (input clk);
|
||||||
reg [7:0] p1;
|
reg [7:0] p1;
|
||||||
reg [7:0] p2;
|
reg [7:0] p2;
|
||||||
reg [7:0] p3;
|
reg [7:0] p3;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,24 +10,24 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
logic [2:0] [1:0] in;
|
logic [2:0] [1:0] in;
|
||||||
always @* in = crc[5:0];
|
always @* in = crc[5:0];
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
logic [1:0] [1:0] out; // From test of Test.v
|
logic [1:0] [1:0] out; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out (out/*[1:0][1:0]*/),
|
.out (out/*[1:0][1:0]*/),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.in (in/*[2:0][1:0]*/));
|
.in (in/*[2:0][1:0]*/));
|
||||||
|
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
wire [63:0] result = {60'h0, out[1],out[0]};
|
wire [63:0] result = {60'h0, out[1],out[0]};
|
||||||
|
|
@ -41,23 +41,23 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
// What checksum will we end up with (above print should match)
|
// What checksum will we end up with (above print should match)
|
||||||
`define EXPECTED_SUM 64'hdc21e42d85441511
|
`define EXPECTED_SUM 64'hdc21e42d85441511
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -30,9 +30,9 @@ module t(/*AUTOARG*/
|
||||||
|
|
||||||
union packed {
|
union packed {
|
||||||
logic [31:0] [7:0] idx;
|
logic [31:0] [7:0] idx;
|
||||||
struct packed {
|
struct packed {
|
||||||
logic [15:0] z, y, x;
|
logic [15:0] z, y, x;
|
||||||
logic [25:0] [7:0] r;
|
logic [25:0] [7:0] r;
|
||||||
} nam;
|
} nam;
|
||||||
} gpr;
|
} gpr;
|
||||||
|
|
||||||
|
|
@ -40,9 +40,9 @@ module t(/*AUTOARG*/
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
b = {16'h8765,16'h4321};
|
b = {16'h8765,16'h4321};
|
||||||
a = b[19:12]; // This works
|
a = b[19:12]; // This works
|
||||||
c = b[8+:8]; // This fails
|
c = b[8+:8]; // This fails
|
||||||
d = b[11-:8]; // This fails
|
d = b[11-:8]; // This fails
|
||||||
`checkh(a, 8'h54);
|
`checkh(a, 8'h54);
|
||||||
`checkh(c, 8'h43);
|
`checkh(c, 8'h43);
|
||||||
`checkh(d, 8'h32);
|
`checkh(d, 8'h32);
|
||||||
|
|
|
||||||
|
|
@ -24,50 +24,50 @@ module t (/*AUTOARG*/
|
||||||
// surefire lint_off STMINI
|
// surefire lint_off STMINI
|
||||||
// surefire lint_off NBAJAM
|
// surefire lint_off NBAJAM
|
||||||
|
|
||||||
always @ (posedge clk) begin // filp-flops with asynchronous reset
|
always @ (posedge clk) begin // filp-flops with asynchronous reset
|
||||||
if (0) begin
|
if (0) begin
|
||||||
_mode <= 0;
|
_mode <= 0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
_mode <= _mode + 1;
|
_mode <= _mode + 1;
|
||||||
if (_mode==0) begin
|
if (_mode==0) begin
|
||||||
$write("[%0t] t_blocking: Running\n", $time);
|
$write("[%0t] t_blocking: Running\n", $time);
|
||||||
a <= 8'd0;
|
a <= 8'd0;
|
||||||
b <= 8'd0;
|
b <= 8'd0;
|
||||||
c <= 8'd0;
|
c <= 8'd0;
|
||||||
end
|
end
|
||||||
else if (_mode==1) begin
|
else if (_mode==1) begin
|
||||||
if (a !== 8'd0) $stop;
|
if (a !== 8'd0) $stop;
|
||||||
if (b !== 8'd0) $stop;
|
if (b !== 8'd0) $stop;
|
||||||
if (c !== 8'd0) $stop;
|
if (c !== 8'd0) $stop;
|
||||||
a <= b;
|
a <= b;
|
||||||
b <= 8'd1;
|
b <= 8'd1;
|
||||||
c <= b;
|
c <= b;
|
||||||
if (a !== 8'd0) $stop;
|
if (a !== 8'd0) $stop;
|
||||||
if (b !== 8'd0) $stop;
|
if (b !== 8'd0) $stop;
|
||||||
if (c !== 8'd0) $stop;
|
if (c !== 8'd0) $stop;
|
||||||
end
|
end
|
||||||
else if (_mode==2) begin
|
else if (_mode==2) begin
|
||||||
if (a !== 8'd0) $stop;
|
if (a !== 8'd0) $stop;
|
||||||
if (b !== 8'd1) $stop;
|
if (b !== 8'd1) $stop;
|
||||||
if (c !== 8'd0) $stop;
|
if (c !== 8'd0) $stop;
|
||||||
a <= b;
|
a <= b;
|
||||||
b <= 8'd2;
|
b <= 8'd2;
|
||||||
c <= b;
|
c <= b;
|
||||||
if (a !== 8'd0) $stop;
|
if (a !== 8'd0) $stop;
|
||||||
if (b !== 8'd1) $stop;
|
if (b !== 8'd1) $stop;
|
||||||
if (c !== 8'd0) $stop;
|
if (c !== 8'd0) $stop;
|
||||||
end
|
end
|
||||||
else if (_mode==3) begin
|
else if (_mode==3) begin
|
||||||
if (a !== 8'd1) $stop;
|
if (a !== 8'd1) $stop;
|
||||||
if (b !== 8'd2) $stop;
|
if (b !== 8'd2) $stop;
|
||||||
if (c !== 8'd1) $stop;
|
if (c !== 8'd1) $stop;
|
||||||
end
|
end
|
||||||
else if (_mode==4) begin
|
else if (_mode==4) begin
|
||||||
if (mode_d3r != 8'd1) $stop;
|
if (mode_d3r != 8'd1) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -81,15 +81,15 @@ module t (/*AUTOARG*/
|
||||||
// surefire lint_off SEQASS
|
// surefire lint_off SEQASS
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (_mode==1) begin
|
if (_mode==1) begin
|
||||||
bits[14:13] <= 2'b11;
|
bits[14:13] <= 2'b11;
|
||||||
bits[12] <= 1'b1;
|
bits[12] <= 1'b1;
|
||||||
end
|
end
|
||||||
if (_mode==2) begin
|
if (_mode==2) begin
|
||||||
bits[11:10] <= 2'b10;
|
bits[11:10] <= 2'b10;
|
||||||
bits[13] <= 0;
|
bits[13] <= 0;
|
||||||
end
|
end
|
||||||
if (_mode==3) begin
|
if (_mode==3) begin
|
||||||
if (bits !== 5'b10110) $stop;
|
if (bits !== 5'b10110) $stop;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -15,12 +15,12 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
case(idx)
|
case(idx)
|
||||||
1: idx = 100;
|
1: idx = 100;
|
||||||
100: begin
|
100: begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -12,35 +12,35 @@ module t (/*AUTOARG*/
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
localparam // synopsys enum En_State
|
localparam // synopsys enum En_State
|
||||||
EP_State_IDLE = {3'b000,5'd00},
|
EP_State_IDLE = {3'b000,5'd00},
|
||||||
EP_State_CMDSHIFT0 = {3'b001,5'd00},
|
EP_State_CMDSHIFT0 = {3'b001,5'd00},
|
||||||
EP_State_CMDSHIFT13 = {3'b001,5'd13},
|
EP_State_CMDSHIFT13 = {3'b001,5'd13},
|
||||||
EP_State_CMDSHIFT14 = {3'b001,5'd14},
|
EP_State_CMDSHIFT14 = {3'b001,5'd14},
|
||||||
EP_State_CMDSHIFT15 = {3'b001,5'd15},
|
EP_State_CMDSHIFT15 = {3'b001,5'd15},
|
||||||
EP_State_CMDSHIFT16 = {3'b001,5'd16},
|
EP_State_CMDSHIFT16 = {3'b001,5'd16},
|
||||||
EP_State_DWAIT = {3'b010,5'd00},
|
EP_State_DWAIT = {3'b010,5'd00},
|
||||||
EP_State_DSHIFT0 = {3'b100,5'd00},
|
EP_State_DSHIFT0 = {3'b100,5'd00},
|
||||||
EP_State_DSHIFT1 = {3'b100,5'd01},
|
EP_State_DSHIFT1 = {3'b100,5'd01},
|
||||||
EP_State_DSHIFT15 = {3'b100,5'd15};
|
EP_State_DSHIFT15 = {3'b100,5'd15};
|
||||||
|
|
||||||
reg [7:0] /* synopsys enum En_State */
|
reg [7:0] /* synopsys enum En_State */
|
||||||
m_state_xr; // Last command, for debugging
|
m_state_xr; // Last command, for debugging
|
||||||
/*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/
|
/*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/
|
||||||
// Beginning of automatic ASCII enum decoding
|
// Beginning of automatic ASCII enum decoding
|
||||||
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
|
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
|
||||||
always @(m_state_xr) begin
|
always @(m_state_xr) begin
|
||||||
case ({m_state_xr})
|
case ({m_state_xr})
|
||||||
EP_State_IDLE: m_stateAscii_xr = "idle ";
|
EP_State_IDLE: m_stateAscii_xr = "idle ";
|
||||||
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
|
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
|
||||||
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
|
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
|
||||||
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
|
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
|
||||||
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
|
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
|
||||||
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
|
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
|
||||||
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
|
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
|
||||||
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
|
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
|
||||||
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
|
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
|
||||||
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
|
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
|
||||||
default: m_stateAscii_xr = "%Error ";
|
default: m_stateAscii_xr = "%Error ";
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
@ -48,28 +48,28 @@ module t (/*AUTOARG*/
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
|
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
m_state_xr <= EP_State_IDLE;
|
m_state_xr <= EP_State_IDLE;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
if (m_stateAscii_xr != "idle ") $stop;
|
if (m_stateAscii_xr != "idle ") $stop;
|
||||||
m_state_xr <= EP_State_CMDSHIFT13;
|
m_state_xr <= EP_State_CMDSHIFT13;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
if (m_stateAscii_xr != "cmdshift13") $stop;
|
if (m_stateAscii_xr != "cmdshift13") $stop;
|
||||||
m_state_xr <= EP_State_CMDSHIFT16;
|
m_state_xr <= EP_State_CMDSHIFT16;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
if (m_stateAscii_xr != "cmdshift16") $stop;
|
if (m_stateAscii_xr != "cmdshift16") $stop;
|
||||||
m_state_xr <= EP_State_DWAIT;
|
m_state_xr <= EP_State_DWAIT;
|
||||||
end
|
end
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
if (m_stateAscii_xr != "dwait ") $stop;
|
if (m_stateAscii_xr != "dwait ") $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,28 +10,28 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire [33:0] in = crc[33:0];
|
wire [33:0] in = crc[33:0];
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [31:0] code; // From test of Test.v
|
wire [31:0] code; // From test of Test.v
|
||||||
wire [4:0] len; // From test of Test.v
|
wire [4:0] len; // From test of Test.v
|
||||||
wire next; // From test of Test.v
|
wire next; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.next (next),
|
.next (next),
|
||||||
.code (code[31:0]),
|
.code (code[31:0]),
|
||||||
.len (len[4:0]),
|
.len (len[4:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.in (in[33:0]));
|
.in (in[33:0]));
|
||||||
|
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
wire [63:0] result = {26'h0, next, len, code};
|
wire [63:0] result = {26'h0, next, len, code};
|
||||||
|
|
@ -48,20 +48,20 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -76,15 +76,15 @@ module Test (/*AUTOARG*/
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
input [33:0] in;
|
input [33:0] in;
|
||||||
output next;
|
output next;
|
||||||
output [31:0] code;
|
output [31:0] code;
|
||||||
output [4:0] len;
|
output [4:0] len;
|
||||||
|
|
||||||
/*AUTOREG*/
|
/*AUTOREG*/
|
||||||
// Beginning of automatic regs (for this module's undeclared outputs)
|
// Beginning of automatic regs (for this module's undeclared outputs)
|
||||||
reg [31:0] code;
|
reg [31:0] code;
|
||||||
reg [4:0] len;
|
reg [4:0] len;
|
||||||
reg next;
|
reg next;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -99,31 +99,31 @@ pat:
|
||||||
my ($try, $val, $mask);
|
my ($try, $val, $mask);
|
||||||
try:
|
try:
|
||||||
for ($try=0; ; $try++) {
|
for ($try=0; ; $try++) {
|
||||||
next pat if $try>50;
|
next pat if $try>50;
|
||||||
$val = 0;
|
$val = 0;
|
||||||
for (my $bit=23; $bit>(23-$len); $bit--) {
|
for (my $bit=23; $bit>(23-$len); $bit--) {
|
||||||
my $b = int(rand()*2);
|
my $b = int(rand()*2);
|
||||||
$val |= (1<<$bit) if $b;
|
$val |= (1<<$bit) if $b;
|
||||||
}
|
}
|
||||||
$mask = (1<<(23-$len+1))-1;
|
$mask = (1<<(23-$len+1))-1;
|
||||||
for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
|
for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
|
||||||
next try if $used[$testval];
|
next try if $used[$testval];
|
||||||
}
|
}
|
||||||
last;
|
last;
|
||||||
}
|
}
|
||||||
my $bits = "";
|
my $bits = "";
|
||||||
my $val2 = 0;
|
my $val2 = 0;
|
||||||
for (my $bit=23; $bit>(23-$len); $bit--) {
|
for (my $bit=23; $bit>(23-$len); $bit--) {
|
||||||
my $b = ($val & (1<<$bit));
|
my $b = ($val & (1<<$bit));
|
||||||
$bits .= $b?'1':'0';
|
$bits .= $b?'1':'0';
|
||||||
}
|
}
|
||||||
for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
|
for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
|
||||||
$used[$testval]= 1; #printf "U%08x\n", $testval;
|
$used[$testval]= 1; #printf "U%08x\n", $testval;
|
||||||
}
|
}
|
||||||
if ($try<90) {
|
if ($try<90) {
|
||||||
printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
|
printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
|
||||||
,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
|
,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
|
||||||
$pat++;
|
$pat++;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
*/
|
*/
|
||||||
|
|
@ -133,211 +133,211 @@ pat:
|
||||||
code = 32'd0;
|
code = 32'd0;
|
||||||
len = 5'b11111;
|
len = 5'b11111;
|
||||||
casez (in[31:8])
|
casez (in[31:8])
|
||||||
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
|
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
|
||||||
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
|
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
|
||||||
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
|
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
|
||||||
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
|
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
|
||||||
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
|
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
|
||||||
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
|
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
|
||||||
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
|
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
|
||||||
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
|
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
|
||||||
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
|
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
|
||||||
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
|
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
|
||||||
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
|
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
|
||||||
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
|
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
|
||||||
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
|
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
|
||||||
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
|
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
|
||||||
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
|
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
|
||||||
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
|
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
|
||||||
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
|
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
|
||||||
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
|
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
|
||||||
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
|
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
|
||||||
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
|
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
|
||||||
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
|
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
|
||||||
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
|
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
|
||||||
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
|
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
|
||||||
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
|
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
|
||||||
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
|
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
|
||||||
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
|
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
|
||||||
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
|
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
|
||||||
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
|
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
|
||||||
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
|
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
|
||||||
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
|
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
|
||||||
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
|
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
|
||||||
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
|
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
|
||||||
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
|
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
|
||||||
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
|
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
|
||||||
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
|
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
|
||||||
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
|
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
|
||||||
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
|
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
|
||||||
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
|
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
|
||||||
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
|
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
|
||||||
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
|
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
|
||||||
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
|
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
|
||||||
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
|
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
|
||||||
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
|
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
|
||||||
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
|
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
|
||||||
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
|
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
|
||||||
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
|
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
|
||||||
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
|
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
|
||||||
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
|
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
|
||||||
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
|
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
|
||||||
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
|
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
|
||||||
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
|
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
|
||||||
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
|
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
|
||||||
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
|
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
|
||||||
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
|
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
|
||||||
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
|
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
|
||||||
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
|
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
|
||||||
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
|
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
|
||||||
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
|
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
|
||||||
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
|
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
|
||||||
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
|
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
|
||||||
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
|
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
|
||||||
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
|
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
|
||||||
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
|
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
|
||||||
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
|
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
|
||||||
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
|
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
|
||||||
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
|
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
|
||||||
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
|
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
|
||||||
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
|
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
|
||||||
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
|
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
|
||||||
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
|
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
|
||||||
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
|
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
|
||||||
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
|
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
|
||||||
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
|
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
|
||||||
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
|
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
|
||||||
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
|
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
|
||||||
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
|
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
|
||||||
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
|
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
|
||||||
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
|
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
|
||||||
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
|
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
|
||||||
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
|
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
|
||||||
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
|
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
|
||||||
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
|
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
|
||||||
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
|
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
|
||||||
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
|
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
|
||||||
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
|
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
|
||||||
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
|
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
|
||||||
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
|
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
|
||||||
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
|
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
|
||||||
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
|
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
|
||||||
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
|
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
|
||||||
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
|
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
|
||||||
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
|
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
|
||||||
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
|
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
|
||||||
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
|
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
|
||||||
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
|
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
|
||||||
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
|
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
|
||||||
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
|
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
|
||||||
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
|
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
|
||||||
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
|
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
|
||||||
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
|
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
|
||||||
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
|
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
|
||||||
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
|
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
|
||||||
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
|
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
|
||||||
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
|
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
|
||||||
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
|
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
|
||||||
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
|
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
|
||||||
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
|
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
|
||||||
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
|
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
|
||||||
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
|
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
|
||||||
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
|
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
|
||||||
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
|
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
|
||||||
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
|
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
|
||||||
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
|
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
|
||||||
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
|
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
|
||||||
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
|
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
|
||||||
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
|
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
|
||||||
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
|
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
|
||||||
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
|
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
|
||||||
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
|
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
|
||||||
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
|
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
|
||||||
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
|
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
|
||||||
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
|
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
|
||||||
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
|
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
|
||||||
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
|
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
|
||||||
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
|
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
|
||||||
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
|
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
|
||||||
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
|
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
|
||||||
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
|
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
|
||||||
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
|
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
|
||||||
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
|
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
|
||||||
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
|
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
|
||||||
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
|
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
|
||||||
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
|
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
|
||||||
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
|
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
|
||||||
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
|
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
|
||||||
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
|
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
|
||||||
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
|
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
|
||||||
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
|
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
|
||||||
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
|
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
|
||||||
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
|
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
|
||||||
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
|
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
|
||||||
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
|
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
|
||||||
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
|
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
|
||||||
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
|
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
|
||||||
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
|
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
|
||||||
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
|
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
|
||||||
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
|
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
|
||||||
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
|
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
|
||||||
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
|
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
|
||||||
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
|
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
|
||||||
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
|
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
|
||||||
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
|
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
|
||||||
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
|
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
|
||||||
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
|
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
|
||||||
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
|
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
|
||||||
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
|
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
|
||||||
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
|
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
|
||||||
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
|
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
|
||||||
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
|
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
|
||||||
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
|
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
|
||||||
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
|
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
|
||||||
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
|
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
|
||||||
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
|
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
|
||||||
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
|
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
|
||||||
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
|
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
|
||||||
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
|
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
|
||||||
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
|
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
|
||||||
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
|
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
|
||||||
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
|
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
|
||||||
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
|
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
|
||||||
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
|
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
|
||||||
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
|
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
|
||||||
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
|
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
|
||||||
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
|
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
|
||||||
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
|
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
|
||||||
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
|
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
|
||||||
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
|
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
|
||||||
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
|
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
|
||||||
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
|
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
|
||||||
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
|
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
|
||||||
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
|
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
|
||||||
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
|
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
|
||||||
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
|
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
|
||||||
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
|
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
|
||||||
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
|
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
|
||||||
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
|
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
|
||||||
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
|
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
|
||||||
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
|
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
|
||||||
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
|
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
|
||||||
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
|
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
|
||||||
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
|
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
|
||||||
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
|
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
|
||||||
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
|
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
|
||||||
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
|
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
|
||||||
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
|
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
|
||||||
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
|
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
|
||||||
24'b000000??????????????????: begin
|
24'b000000??????????????????: begin
|
||||||
casez (in[33:32])
|
casez (in[33:32])
|
||||||
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
|
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
|
||||||
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
|
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
|
||||||
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
|
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
|
||||||
default: ;
|
default: ;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
default: ;
|
default: ;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -10,23 +10,23 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire [1:0] in = crc[1:0];
|
wire [1:0] in = crc[1:0];
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [1:0] out; // From test of Test.v
|
wire [1:0] out; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out (out[1:0]),
|
.out (out[1:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.in (in[1:0]));
|
.in (in[1:0]));
|
||||||
|
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
wire [63:0] result = {62'h0, out};
|
wire [63:0] result = {62'h0, out};
|
||||||
|
|
@ -43,20 +43,20 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -73,9 +73,9 @@ module Test (/*AUTOARG*/
|
||||||
always @* begin
|
always @* begin
|
||||||
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
|
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
|
||||||
case (in[1:0])
|
case (in[1:0])
|
||||||
2'd0, 2'd1, 2'd2, 2'd3: begin
|
2'd0, 2'd1, 2'd2, 2'd3: begin
|
||||||
out = in;
|
out = in;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -6,8 +6,8 @@
|
||||||
|
|
||||||
module t
|
module t
|
||||||
(
|
(
|
||||||
input i_clk,
|
input i_clk,
|
||||||
input [6:0] i_input,
|
input [6:0] i_input,
|
||||||
output logic o_output
|
output logic o_output
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -23,118 +23,118 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [9:0] outa0; // From s0 of t_case_huge_sub.v
|
wire [9:0] outa0; // From s0 of t_case_huge_sub.v
|
||||||
wire [9:0] outa1; // From s1 of t_case_huge_sub.v
|
wire [9:0] outa1; // From s1 of t_case_huge_sub.v
|
||||||
wire [9:0] outa2; // From s2 of t_case_huge_sub.v
|
wire [9:0] outa2; // From s2 of t_case_huge_sub.v
|
||||||
wire [9:0] outa3; // From s3 of t_case_huge_sub.v
|
wire [9:0] outa3; // From s3 of t_case_huge_sub.v
|
||||||
wire [9:0] outa4; // From s4 of t_case_huge_sub.v
|
wire [9:0] outa4; // From s4 of t_case_huge_sub.v
|
||||||
wire [9:0] outa5; // From s5 of t_case_huge_sub.v
|
wire [9:0] outa5; // From s5 of t_case_huge_sub.v
|
||||||
wire [9:0] outa6; // From s6 of t_case_huge_sub.v
|
wire [9:0] outa6; // From s6 of t_case_huge_sub.v
|
||||||
wire [9:0] outa7; // From s7 of t_case_huge_sub.v
|
wire [9:0] outa7; // From s7 of t_case_huge_sub.v
|
||||||
wire [1:0] outb0; // From s0 of t_case_huge_sub.v
|
wire [1:0] outb0; // From s0 of t_case_huge_sub.v
|
||||||
wire [1:0] outb1; // From s1 of t_case_huge_sub.v
|
wire [1:0] outb1; // From s1 of t_case_huge_sub.v
|
||||||
wire [1:0] outb2; // From s2 of t_case_huge_sub.v
|
wire [1:0] outb2; // From s2 of t_case_huge_sub.v
|
||||||
wire [1:0] outb3; // From s3 of t_case_huge_sub.v
|
wire [1:0] outb3; // From s3 of t_case_huge_sub.v
|
||||||
wire [1:0] outb4; // From s4 of t_case_huge_sub.v
|
wire [1:0] outb4; // From s4 of t_case_huge_sub.v
|
||||||
wire [1:0] outb5; // From s5 of t_case_huge_sub.v
|
wire [1:0] outb5; // From s5 of t_case_huge_sub.v
|
||||||
wire [1:0] outb6; // From s6 of t_case_huge_sub.v
|
wire [1:0] outb6; // From s6 of t_case_huge_sub.v
|
||||||
wire [1:0] outb7; // From s7 of t_case_huge_sub.v
|
wire [1:0] outb7; // From s7 of t_case_huge_sub.v
|
||||||
wire outc0; // From s0 of t_case_huge_sub.v
|
wire outc0; // From s0 of t_case_huge_sub.v
|
||||||
wire outc1; // From s1 of t_case_huge_sub.v
|
wire outc1; // From s1 of t_case_huge_sub.v
|
||||||
wire outc2; // From s2 of t_case_huge_sub.v
|
wire outc2; // From s2 of t_case_huge_sub.v
|
||||||
wire outc3; // From s3 of t_case_huge_sub.v
|
wire outc3; // From s3 of t_case_huge_sub.v
|
||||||
wire outc4; // From s4 of t_case_huge_sub.v
|
wire outc4; // From s4 of t_case_huge_sub.v
|
||||||
wire outc5; // From s5 of t_case_huge_sub.v
|
wire outc5; // From s5 of t_case_huge_sub.v
|
||||||
wire outc6; // From s6 of t_case_huge_sub.v
|
wire outc6; // From s6 of t_case_huge_sub.v
|
||||||
wire outc7; // From s7 of t_case_huge_sub.v
|
wire outc7; // From s7 of t_case_huge_sub.v
|
||||||
wire [9:0] outq; // From q of t_case_huge_sub4.v
|
wire [9:0] outq; // From q of t_case_huge_sub4.v
|
||||||
wire [3:0] outr; // From sub3 of t_case_huge_sub3.v
|
wire [3:0] outr; // From sub3 of t_case_huge_sub3.v
|
||||||
wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v
|
wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
t_case_huge_sub2 sub2 (
|
t_case_huge_sub2 sub2 (
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outsmall[9:0]),
|
.outa (outsmall[9:0]),
|
||||||
/*AUTOINST*/
|
/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index[9:0]));
|
.index (index[9:0]));
|
||||||
|
|
||||||
t_case_huge_sub3 sub3 (/*AUTOINST*/
|
t_case_huge_sub3 sub3 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outr (outr[3:0]),
|
.outr (outr[3:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.index (index[9:0]));
|
.index (index[9:0]));
|
||||||
|
|
||||||
/* t_case_huge_sub AUTO_TEMPLATE (
|
/* t_case_huge_sub AUTO_TEMPLATE (
|
||||||
.outa (outa@[]),
|
.outa (outa@[]),
|
||||||
.outb (outb@[]),
|
.outb (outb@[]),
|
||||||
.outc (outc@[]),
|
.outc (outc@[]),
|
||||||
.index (index@[]));
|
.index (index@[]));
|
||||||
*/
|
*/
|
||||||
|
|
||||||
t_case_huge_sub s0 (/*AUTOINST*/
|
t_case_huge_sub s0 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa0[9:0]), // Templated
|
.outa (outa0[9:0]), // Templated
|
||||||
.outb (outb0[1:0]), // Templated
|
.outb (outb0[1:0]), // Templated
|
||||||
.outc (outc0), // Templated
|
.outc (outc0), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index0[7:0])); // Templated
|
.index (index0[7:0])); // Templated
|
||||||
t_case_huge_sub s1 (/*AUTOINST*/
|
t_case_huge_sub s1 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa1[9:0]), // Templated
|
.outa (outa1[9:0]), // Templated
|
||||||
.outb (outb1[1:0]), // Templated
|
.outb (outb1[1:0]), // Templated
|
||||||
.outc (outc1), // Templated
|
.outc (outc1), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index1[7:0])); // Templated
|
.index (index1[7:0])); // Templated
|
||||||
t_case_huge_sub s2 (/*AUTOINST*/
|
t_case_huge_sub s2 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa2[9:0]), // Templated
|
.outa (outa2[9:0]), // Templated
|
||||||
.outb (outb2[1:0]), // Templated
|
.outb (outb2[1:0]), // Templated
|
||||||
.outc (outc2), // Templated
|
.outc (outc2), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index2[7:0])); // Templated
|
.index (index2[7:0])); // Templated
|
||||||
t_case_huge_sub s3 (/*AUTOINST*/
|
t_case_huge_sub s3 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa3[9:0]), // Templated
|
.outa (outa3[9:0]), // Templated
|
||||||
.outb (outb3[1:0]), // Templated
|
.outb (outb3[1:0]), // Templated
|
||||||
.outc (outc3), // Templated
|
.outc (outc3), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index3[7:0])); // Templated
|
.index (index3[7:0])); // Templated
|
||||||
t_case_huge_sub s4 (/*AUTOINST*/
|
t_case_huge_sub s4 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa4[9:0]), // Templated
|
.outa (outa4[9:0]), // Templated
|
||||||
.outb (outb4[1:0]), // Templated
|
.outb (outb4[1:0]), // Templated
|
||||||
.outc (outc4), // Templated
|
.outc (outc4), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index4[7:0])); // Templated
|
.index (index4[7:0])); // Templated
|
||||||
t_case_huge_sub s5 (/*AUTOINST*/
|
t_case_huge_sub s5 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa5[9:0]), // Templated
|
.outa (outa5[9:0]), // Templated
|
||||||
.outb (outb5[1:0]), // Templated
|
.outb (outb5[1:0]), // Templated
|
||||||
.outc (outc5), // Templated
|
.outc (outc5), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index5[7:0])); // Templated
|
.index (index5[7:0])); // Templated
|
||||||
t_case_huge_sub s6 (/*AUTOINST*/
|
t_case_huge_sub s6 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa6[9:0]), // Templated
|
.outa (outa6[9:0]), // Templated
|
||||||
.outb (outb6[1:0]), // Templated
|
.outb (outb6[1:0]), // Templated
|
||||||
.outc (outc6), // Templated
|
.outc (outc6), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index6[7:0])); // Templated
|
.index (index6[7:0])); // Templated
|
||||||
t_case_huge_sub s7 (/*AUTOINST*/
|
t_case_huge_sub s7 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outa (outa7[9:0]), // Templated
|
.outa (outa7[9:0]), // Templated
|
||||||
.outb (outb7[1:0]), // Templated
|
.outb (outb7[1:0]), // Templated
|
||||||
.outc (outc7), // Templated
|
.outc (outc7), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index7[7:0])); // Templated
|
.index (index7[7:0])); // Templated
|
||||||
|
|
||||||
t_case_huge_sub4 q (/*AUTOINST*/
|
t_case_huge_sub4 q (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.outq (outq[9:0]),
|
.outq (outq[9:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.index (index[7:0]));
|
.index (index[7:0]));
|
||||||
|
|
||||||
|
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
|
|
@ -142,69 +142,69 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
//$write("%x: %x\n",cyc,outr);
|
//$write("%x: %x\n",cyc,outr);
|
||||||
//$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1);
|
//$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1);
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
index <= 10'h236;
|
index <= 10'h236;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
index <= 10'h022;
|
index <= 10'h022;
|
||||||
if (outsmall != 10'h282) $stop;
|
if (outsmall != 10'h282) $stop;
|
||||||
if (outr != 4'b0) $stop;
|
if (outr != 4'b0) $stop;
|
||||||
if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop;
|
if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop;
|
||||||
if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop;
|
if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop;
|
||||||
if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop;
|
if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop;
|
||||||
if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop;
|
if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop;
|
||||||
if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop;
|
if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop;
|
||||||
if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop;
|
if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop;
|
||||||
if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop;
|
if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop;
|
||||||
if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop;
|
if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop;
|
||||||
if (outq != 10'h001) $stop;
|
if (outq != 10'h001) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
index <= 10'h165;
|
index <= 10'h165;
|
||||||
if (outsmall != 10'h191) $stop;
|
if (outsmall != 10'h191) $stop;
|
||||||
if (outr != 4'h5) $stop;
|
if (outr != 4'h5) $stop;
|
||||||
if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop;
|
if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop;
|
||||||
if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop;
|
if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop;
|
||||||
if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop;
|
if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop;
|
||||||
if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop;
|
if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop;
|
||||||
if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop;
|
if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop;
|
||||||
if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop;
|
if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop;
|
||||||
if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop;
|
if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop;
|
||||||
if (outq != 10'h001) $stop;
|
if (outq != 10'h001) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
index <= 10'h201;
|
index <= 10'h201;
|
||||||
if (outsmall != 10'h268) $stop;
|
if (outsmall != 10'h268) $stop;
|
||||||
if (outr != 4'h2) $stop;
|
if (outr != 4'h2) $stop;
|
||||||
if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop;
|
if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop;
|
||||||
if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop;
|
if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop;
|
||||||
if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop;
|
if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop;
|
||||||
if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop;
|
if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop;
|
||||||
if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop;
|
if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop;
|
||||||
if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop;
|
if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop;
|
||||||
if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop;
|
if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop;
|
||||||
if (outq != 10'h001) $stop;
|
if (outq != 10'h001) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==5) begin
|
if (cyc==5) begin
|
||||||
index <= 10'h3ff;
|
index <= 10'h3ff;
|
||||||
if (outr != 4'hd) $stop;
|
if (outr != 4'hd) $stop;
|
||||||
if (outq != 10'h001) $stop;
|
if (outq != 10'h001) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==6) begin
|
if (cyc==6) begin
|
||||||
index <= 10'h0;
|
index <= 10'h0;
|
||||||
if (outr != 4'hd) $stop;
|
if (outr != 4'hd) $stop;
|
||||||
if (outq != 10'h114) $stop;
|
if (outq != 10'h114) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==7) begin
|
if (cyc==7) begin
|
||||||
if (outr != 4'h4) $stop;
|
if (outr != 4'h4) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -14,14 +14,14 @@ module t_case_huge_sub (/*AUTOARG*/
|
||||||
input [7:0] index;
|
input [7:0] index;
|
||||||
output [9:0] outa;
|
output [9:0] outa;
|
||||||
output [1:0] outb;
|
output [1:0] outb;
|
||||||
output outc;
|
output outc;
|
||||||
|
|
||||||
// =============================
|
// =============================
|
||||||
/*AUTOREG*/
|
/*AUTOREG*/
|
||||||
// Beginning of automatic regs (for this module's undeclared outputs)
|
// Beginning of automatic regs (for this module's undeclared outputs)
|
||||||
reg [9:0] outa;
|
reg [9:0] outa;
|
||||||
reg [1:0] outb;
|
reg [1:0] outb;
|
||||||
reg outc;
|
reg outc;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
// =============================
|
// =============================
|
||||||
|
|
@ -30,262 +30,262 @@ module t_case_huge_sub (/*AUTOARG*/
|
||||||
|
|
||||||
always @(/*AS*/index) begin
|
always @(/*AS*/index) begin
|
||||||
case (index)
|
case (index)
|
||||||
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
|
8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
|
8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
|
8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
|
8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
|
8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
|
8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
|
8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
|
8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
|
8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
|
8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
|
8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
|
8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
|
8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
|
8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
|
8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
|
8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
|
8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
|
8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
|
8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
|
8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
|
8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
|
8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
|
8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
|
8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
|
8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
|
8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
|
8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
|
8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
|
8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
|
8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
|
8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
|
8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
|
8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
|
8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
|
8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
|
8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
|
8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
|
8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
|
8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
|
8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
|
8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
|
8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
|
8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
|
8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
|
8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
|
8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
|
8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
|
8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
|
8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
|
8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
|
8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
|
8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
|
8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
|
8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
|
8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
|
8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
|
8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
|
8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
|
8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
|
8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
|
8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
|
8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
|
8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
|
8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
|
8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
|
8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
|
8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
|
8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
|
8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
|
8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
|
8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
|
8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
|
8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
|
8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
|
8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
|
8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
|
8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
|
8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
|
8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
|
8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
|
8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
|
8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
|
8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
|
8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
|
8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
|
8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
|
8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
|
8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
|
8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
|
8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
|
8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
|
8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
|
8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
|
8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
|
8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
|
8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
|
8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
|
8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
|
8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
|
8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
|
8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
|
8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
|
8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
|
8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
|
8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
|
8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
|
8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
|
8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
|
8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
|
8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
|
8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
|
8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
|
8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
|
8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
|
8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
|
8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
|
8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
|
8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
|
8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
|
8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
|
8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
|
8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
|
8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end
|
||||||
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
|
8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
|
8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
|
8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
|
8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
|
8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
|
8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
|
8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
|
8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
|
8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
|
8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
|
8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
|
8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
|
8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
|
8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
|
8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
|
8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
|
8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end
|
||||||
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
|
8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
|
8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
|
8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
|
8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
|
8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
|
8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
|
8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
|
8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
|
8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
|
8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end
|
||||||
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
|
8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
|
8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end
|
||||||
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
|
8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end
|
||||||
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
|
8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
|
8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
|
8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end
|
||||||
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
|
8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end
|
||||||
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
|
8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
|
8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end
|
||||||
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
|
8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end
|
||||||
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
|
8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end
|
||||||
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
|
8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end
|
||||||
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
|
8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end
|
||||||
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
|
8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end
|
||||||
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
|
8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end
|
||||||
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
|
8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end
|
||||||
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
|
8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end
|
||||||
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
|
8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end
|
||||||
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
|
8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end
|
||||||
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
|
8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end
|
||||||
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
|
8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
|
8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end
|
||||||
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
|
8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end
|
||||||
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
|
8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
|
8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end
|
||||||
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
|
8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end
|
||||||
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
|
8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
|
8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
|
8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
|
8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
|
8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end
|
||||||
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
|
8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
|
8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end
|
||||||
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
|
8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
|
8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
|
8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
|
8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
|
8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
|
8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
|
8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
|
8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
|
8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
|
8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
|
8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
|
8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
|
8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end
|
||||||
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
|
8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
|
8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
|
8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end
|
||||||
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
|
8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end
|
||||||
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
|
8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end
|
||||||
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
|
8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
|
8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end
|
||||||
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
|
8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
|
8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
|
8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
|
8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
|
8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
|
8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
|
8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
|
8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
|
8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
|
8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
|
8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
|
8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
|
8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
|
8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
|
8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
|
8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
|
8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
|
8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
|
8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
|
8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
|
8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end
|
||||||
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
|
8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end
|
||||||
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
|
8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end
|
||||||
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
|
8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end
|
||||||
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
|
8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end
|
||||||
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
|
8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end
|
||||||
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
|
8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end
|
||||||
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
|
8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end
|
||||||
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
|
8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end
|
||||||
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
|
8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end
|
||||||
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
|
8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
|
8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end
|
||||||
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
|
8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
|
8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
|
8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
|
8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
|
8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end
|
||||||
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
|
8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end
|
||||||
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
|
8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
|
8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
|
8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end
|
||||||
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
|
8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
|
8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end
|
||||||
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
|
8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
|
8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
|
8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end
|
||||||
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
|
8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
|
8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end
|
||||||
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
|
8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
|
8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end
|
||||||
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
|
8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end
|
||||||
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
|
8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end
|
||||||
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
|
8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -17,7 +17,7 @@ module t_case_huge_sub2 (/*AUTOARG*/
|
||||||
// =============================
|
// =============================
|
||||||
/*AUTOREG*/
|
/*AUTOREG*/
|
||||||
// Beginning of automatic regs (for this module's undeclared outputs)
|
// Beginning of automatic regs (for this module's undeclared outputs)
|
||||||
reg [9:0] outa;
|
reg [9:0] outa;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
// =============================
|
// =============================
|
||||||
|
|
@ -27,265 +27,265 @@ module t_case_huge_sub2 (/*AUTOARG*/
|
||||||
always @(/*AS*/index) begin
|
always @(/*AS*/index) begin
|
||||||
case (index[7:0])
|
case (index[7:0])
|
||||||
`ifdef VERILATOR // Harder test
|
`ifdef VERILATOR // Harder test
|
||||||
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
|
8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable
|
||||||
`else
|
`else
|
||||||
8'h00: begin outa = 10'h0; end
|
8'h00: begin outa = 10'h0; end
|
||||||
`endif
|
`endif
|
||||||
8'h01: begin outa = 10'h318; end
|
8'h01: begin outa = 10'h318; end
|
||||||
8'h02: begin outa = 10'h29f; end
|
8'h02: begin outa = 10'h29f; end
|
||||||
8'h03: begin outa = 10'h392; end
|
8'h03: begin outa = 10'h392; end
|
||||||
8'h04: begin outa = 10'h1ef; end
|
8'h04: begin outa = 10'h1ef; end
|
||||||
8'h05: begin outa = 10'h06c; end
|
8'h05: begin outa = 10'h06c; end
|
||||||
8'h06: begin outa = 10'h29f; end
|
8'h06: begin outa = 10'h29f; end
|
||||||
8'h07: begin outa = 10'h29a; end
|
8'h07: begin outa = 10'h29a; end
|
||||||
8'h08: begin outa = 10'h3ce; end
|
8'h08: begin outa = 10'h3ce; end
|
||||||
8'h09: begin outa = 10'h37c; end
|
8'h09: begin outa = 10'h37c; end
|
||||||
8'h0a: begin outa = 10'h058; end
|
8'h0a: begin outa = 10'h058; end
|
||||||
8'h0b: begin outa = 10'h3b2; end
|
8'h0b: begin outa = 10'h3b2; end
|
||||||
8'h0c: begin outa = 10'h36f; end
|
8'h0c: begin outa = 10'h36f; end
|
||||||
8'h0d: begin outa = 10'h2c5; end
|
8'h0d: begin outa = 10'h2c5; end
|
||||||
8'h0e: begin outa = 10'h23a; end
|
8'h0e: begin outa = 10'h23a; end
|
||||||
8'h0f: begin outa = 10'h222; end
|
8'h0f: begin outa = 10'h222; end
|
||||||
8'h10: begin outa = 10'h328; end
|
8'h10: begin outa = 10'h328; end
|
||||||
8'h11: begin outa = 10'h3c3; end
|
8'h11: begin outa = 10'h3c3; end
|
||||||
8'h12: begin outa = 10'h12c; end
|
8'h12: begin outa = 10'h12c; end
|
||||||
8'h13: begin outa = 10'h1d0; end
|
8'h13: begin outa = 10'h1d0; end
|
||||||
8'h14: begin outa = 10'h3ff; end
|
8'h14: begin outa = 10'h3ff; end
|
||||||
8'h15: begin outa = 10'h115; end
|
8'h15: begin outa = 10'h115; end
|
||||||
8'h16: begin outa = 10'h3ba; end
|
8'h16: begin outa = 10'h3ba; end
|
||||||
8'h17: begin outa = 10'h3ba; end
|
8'h17: begin outa = 10'h3ba; end
|
||||||
8'h18: begin outa = 10'h10d; end
|
8'h18: begin outa = 10'h10d; end
|
||||||
8'h19: begin outa = 10'h13b; end
|
8'h19: begin outa = 10'h13b; end
|
||||||
8'h1a: begin outa = 10'h0a0; end
|
8'h1a: begin outa = 10'h0a0; end
|
||||||
8'h1b: begin outa = 10'h264; end
|
8'h1b: begin outa = 10'h264; end
|
||||||
8'h1c: begin outa = 10'h3a2; end
|
8'h1c: begin outa = 10'h3a2; end
|
||||||
8'h1d: begin outa = 10'h07c; end
|
8'h1d: begin outa = 10'h07c; end
|
||||||
8'h1e: begin outa = 10'h291; end
|
8'h1e: begin outa = 10'h291; end
|
||||||
8'h1f: begin outa = 10'h1d1; end
|
8'h1f: begin outa = 10'h1d1; end
|
||||||
8'h20: begin outa = 10'h354; end
|
8'h20: begin outa = 10'h354; end
|
||||||
8'h21: begin outa = 10'h0c0; end
|
8'h21: begin outa = 10'h0c0; end
|
||||||
8'h22: begin outa = 10'h191; end
|
8'h22: begin outa = 10'h191; end
|
||||||
8'h23: begin outa = 10'h379; end
|
8'h23: begin outa = 10'h379; end
|
||||||
8'h24: begin outa = 10'h073; end
|
8'h24: begin outa = 10'h073; end
|
||||||
8'h25: begin outa = 10'h2fd; end
|
8'h25: begin outa = 10'h2fd; end
|
||||||
8'h26: begin outa = 10'h2e0; end
|
8'h26: begin outa = 10'h2e0; end
|
||||||
8'h27: begin outa = 10'h337; end
|
8'h27: begin outa = 10'h337; end
|
||||||
8'h28: begin outa = 10'h2c7; end
|
8'h28: begin outa = 10'h2c7; end
|
||||||
8'h29: begin outa = 10'h19e; end
|
8'h29: begin outa = 10'h19e; end
|
||||||
8'h2a: begin outa = 10'h107; end
|
8'h2a: begin outa = 10'h107; end
|
||||||
8'h2b: begin outa = 10'h06a; end
|
8'h2b: begin outa = 10'h06a; end
|
||||||
8'h2c: begin outa = 10'h1c7; end
|
8'h2c: begin outa = 10'h1c7; end
|
||||||
8'h2d: begin outa = 10'h107; end
|
8'h2d: begin outa = 10'h107; end
|
||||||
8'h2e: begin outa = 10'h0cf; end
|
8'h2e: begin outa = 10'h0cf; end
|
||||||
8'h2f: begin outa = 10'h009; end
|
8'h2f: begin outa = 10'h009; end
|
||||||
8'h30: begin outa = 10'h09d; end
|
8'h30: begin outa = 10'h09d; end
|
||||||
8'h31: begin outa = 10'h28e; end
|
8'h31: begin outa = 10'h28e; end
|
||||||
8'h32: begin outa = 10'h010; end
|
8'h32: begin outa = 10'h010; end
|
||||||
8'h33: begin outa = 10'h1e0; end
|
8'h33: begin outa = 10'h1e0; end
|
||||||
8'h34: begin outa = 10'h079; end
|
8'h34: begin outa = 10'h079; end
|
||||||
8'h35: begin outa = 10'h13e; end
|
8'h35: begin outa = 10'h13e; end
|
||||||
8'h36: begin outa = 10'h282; end
|
8'h36: begin outa = 10'h282; end
|
||||||
8'h37: begin outa = 10'h21c; end
|
8'h37: begin outa = 10'h21c; end
|
||||||
8'h38: begin outa = 10'h148; end
|
8'h38: begin outa = 10'h148; end
|
||||||
8'h39: begin outa = 10'h3c0; end
|
8'h39: begin outa = 10'h3c0; end
|
||||||
8'h3a: begin outa = 10'h176; end
|
8'h3a: begin outa = 10'h176; end
|
||||||
8'h3b: begin outa = 10'h3fc; end
|
8'h3b: begin outa = 10'h3fc; end
|
||||||
8'h3c: begin outa = 10'h295; end
|
8'h3c: begin outa = 10'h295; end
|
||||||
8'h3d: begin outa = 10'h113; end
|
8'h3d: begin outa = 10'h113; end
|
||||||
8'h3e: begin outa = 10'h354; end
|
8'h3e: begin outa = 10'h354; end
|
||||||
8'h3f: begin outa = 10'h0db; end
|
8'h3f: begin outa = 10'h0db; end
|
||||||
8'h40: begin outa = 10'h238; end
|
8'h40: begin outa = 10'h238; end
|
||||||
8'h41: begin outa = 10'h12b; end
|
8'h41: begin outa = 10'h12b; end
|
||||||
8'h42: begin outa = 10'h1dc; end
|
8'h42: begin outa = 10'h1dc; end
|
||||||
8'h43: begin outa = 10'h137; end
|
8'h43: begin outa = 10'h137; end
|
||||||
8'h44: begin outa = 10'h1e2; end
|
8'h44: begin outa = 10'h1e2; end
|
||||||
8'h45: begin outa = 10'h3d5; end
|
8'h45: begin outa = 10'h3d5; end
|
||||||
8'h46: begin outa = 10'h30c; end
|
8'h46: begin outa = 10'h30c; end
|
||||||
8'h47: begin outa = 10'h298; end
|
8'h47: begin outa = 10'h298; end
|
||||||
8'h48: begin outa = 10'h080; end
|
8'h48: begin outa = 10'h080; end
|
||||||
8'h49: begin outa = 10'h35a; end
|
8'h49: begin outa = 10'h35a; end
|
||||||
8'h4a: begin outa = 10'h01b; end
|
8'h4a: begin outa = 10'h01b; end
|
||||||
8'h4b: begin outa = 10'h0a3; end
|
8'h4b: begin outa = 10'h0a3; end
|
||||||
8'h4c: begin outa = 10'h0b3; end
|
8'h4c: begin outa = 10'h0b3; end
|
||||||
8'h4d: begin outa = 10'h17a; end
|
8'h4d: begin outa = 10'h17a; end
|
||||||
8'h4e: begin outa = 10'h3ae; end
|
8'h4e: begin outa = 10'h3ae; end
|
||||||
8'h4f: begin outa = 10'h078; end
|
8'h4f: begin outa = 10'h078; end
|
||||||
8'h50: begin outa = 10'h322; end
|
8'h50: begin outa = 10'h322; end
|
||||||
8'h51: begin outa = 10'h213; end
|
8'h51: begin outa = 10'h213; end
|
||||||
8'h52: begin outa = 10'h11a; end
|
8'h52: begin outa = 10'h11a; end
|
||||||
8'h53: begin outa = 10'h1a7; end
|
8'h53: begin outa = 10'h1a7; end
|
||||||
8'h54: begin outa = 10'h35a; end
|
8'h54: begin outa = 10'h35a; end
|
||||||
8'h55: begin outa = 10'h233; end
|
8'h55: begin outa = 10'h233; end
|
||||||
8'h56: begin outa = 10'h01d; end
|
8'h56: begin outa = 10'h01d; end
|
||||||
8'h57: begin outa = 10'h2d5; end
|
8'h57: begin outa = 10'h2d5; end
|
||||||
8'h58: begin outa = 10'h1a0; end
|
8'h58: begin outa = 10'h1a0; end
|
||||||
8'h59: begin outa = 10'h3d0; end
|
8'h59: begin outa = 10'h3d0; end
|
||||||
8'h5a: begin outa = 10'h181; end
|
8'h5a: begin outa = 10'h181; end
|
||||||
8'h5b: begin outa = 10'h219; end
|
8'h5b: begin outa = 10'h219; end
|
||||||
8'h5c: begin outa = 10'h26a; end
|
8'h5c: begin outa = 10'h26a; end
|
||||||
8'h5d: begin outa = 10'h050; end
|
8'h5d: begin outa = 10'h050; end
|
||||||
8'h5e: begin outa = 10'h189; end
|
8'h5e: begin outa = 10'h189; end
|
||||||
8'h5f: begin outa = 10'h1eb; end
|
8'h5f: begin outa = 10'h1eb; end
|
||||||
8'h60: begin outa = 10'h224; end
|
8'h60: begin outa = 10'h224; end
|
||||||
8'h61: begin outa = 10'h2fe; end
|
8'h61: begin outa = 10'h2fe; end
|
||||||
8'h62: begin outa = 10'h0ae; end
|
8'h62: begin outa = 10'h0ae; end
|
||||||
8'h63: begin outa = 10'h1cd; end
|
8'h63: begin outa = 10'h1cd; end
|
||||||
8'h64: begin outa = 10'h273; end
|
8'h64: begin outa = 10'h273; end
|
||||||
8'h65: begin outa = 10'h268; end
|
8'h65: begin outa = 10'h268; end
|
||||||
8'h66: begin outa = 10'h111; end
|
8'h66: begin outa = 10'h111; end
|
||||||
8'h67: begin outa = 10'h1f9; end
|
8'h67: begin outa = 10'h1f9; end
|
||||||
8'h68: begin outa = 10'h232; end
|
8'h68: begin outa = 10'h232; end
|
||||||
8'h69: begin outa = 10'h255; end
|
8'h69: begin outa = 10'h255; end
|
||||||
8'h6a: begin outa = 10'h34c; end
|
8'h6a: begin outa = 10'h34c; end
|
||||||
8'h6b: begin outa = 10'h049; end
|
8'h6b: begin outa = 10'h049; end
|
||||||
8'h6c: begin outa = 10'h197; end
|
8'h6c: begin outa = 10'h197; end
|
||||||
8'h6d: begin outa = 10'h0fe; end
|
8'h6d: begin outa = 10'h0fe; end
|
||||||
8'h6e: begin outa = 10'h253; end
|
8'h6e: begin outa = 10'h253; end
|
||||||
8'h6f: begin outa = 10'h2de; end
|
8'h6f: begin outa = 10'h2de; end
|
||||||
8'h70: begin outa = 10'h13b; end
|
8'h70: begin outa = 10'h13b; end
|
||||||
8'h71: begin outa = 10'h040; end
|
8'h71: begin outa = 10'h040; end
|
||||||
8'h72: begin outa = 10'h0b4; end
|
8'h72: begin outa = 10'h0b4; end
|
||||||
8'h73: begin outa = 10'h233; end
|
8'h73: begin outa = 10'h233; end
|
||||||
8'h74: begin outa = 10'h198; end
|
8'h74: begin outa = 10'h198; end
|
||||||
8'h75: begin outa = 10'h018; end
|
8'h75: begin outa = 10'h018; end
|
||||||
8'h76: begin outa = 10'h2f7; end
|
8'h76: begin outa = 10'h2f7; end
|
||||||
8'h77: begin outa = 10'h134; end
|
8'h77: begin outa = 10'h134; end
|
||||||
8'h78: begin outa = 10'h1ca; end
|
8'h78: begin outa = 10'h1ca; end
|
||||||
8'h79: begin outa = 10'h286; end
|
8'h79: begin outa = 10'h286; end
|
||||||
8'h7a: begin outa = 10'h0e6; end
|
8'h7a: begin outa = 10'h0e6; end
|
||||||
8'h7b: begin outa = 10'h064; end
|
8'h7b: begin outa = 10'h064; end
|
||||||
8'h7c: begin outa = 10'h257; end
|
8'h7c: begin outa = 10'h257; end
|
||||||
8'h7d: begin outa = 10'h31a; end
|
8'h7d: begin outa = 10'h31a; end
|
||||||
8'h7e: begin outa = 10'h247; end
|
8'h7e: begin outa = 10'h247; end
|
||||||
8'h7f: begin outa = 10'h299; end
|
8'h7f: begin outa = 10'h299; end
|
||||||
8'h80: begin outa = 10'h02c; end
|
8'h80: begin outa = 10'h02c; end
|
||||||
8'h81: begin outa = 10'h2bb; end
|
8'h81: begin outa = 10'h2bb; end
|
||||||
8'h82: begin outa = 10'h180; end
|
8'h82: begin outa = 10'h180; end
|
||||||
8'h83: begin outa = 10'h245; end
|
8'h83: begin outa = 10'h245; end
|
||||||
8'h84: begin outa = 10'h0da; end
|
8'h84: begin outa = 10'h0da; end
|
||||||
8'h85: begin outa = 10'h367; end
|
8'h85: begin outa = 10'h367; end
|
||||||
8'h86: begin outa = 10'h304; end
|
8'h86: begin outa = 10'h304; end
|
||||||
8'h87: begin outa = 10'h38b; end
|
8'h87: begin outa = 10'h38b; end
|
||||||
8'h88: begin outa = 10'h09f; end
|
8'h88: begin outa = 10'h09f; end
|
||||||
8'h89: begin outa = 10'h1f0; end
|
8'h89: begin outa = 10'h1f0; end
|
||||||
8'h8a: begin outa = 10'h281; end
|
8'h8a: begin outa = 10'h281; end
|
||||||
8'h8b: begin outa = 10'h019; end
|
8'h8b: begin outa = 10'h019; end
|
||||||
8'h8c: begin outa = 10'h1f2; end
|
8'h8c: begin outa = 10'h1f2; end
|
||||||
8'h8d: begin outa = 10'h0b1; end
|
8'h8d: begin outa = 10'h0b1; end
|
||||||
8'h8e: begin outa = 10'h058; end
|
8'h8e: begin outa = 10'h058; end
|
||||||
8'h8f: begin outa = 10'h39b; end
|
8'h8f: begin outa = 10'h39b; end
|
||||||
8'h90: begin outa = 10'h2ec; end
|
8'h90: begin outa = 10'h2ec; end
|
||||||
8'h91: begin outa = 10'h250; end
|
8'h91: begin outa = 10'h250; end
|
||||||
8'h92: begin outa = 10'h3f4; end
|
8'h92: begin outa = 10'h3f4; end
|
||||||
8'h93: begin outa = 10'h057; end
|
8'h93: begin outa = 10'h057; end
|
||||||
8'h94: begin outa = 10'h18f; end
|
8'h94: begin outa = 10'h18f; end
|
||||||
8'h95: begin outa = 10'h105; end
|
8'h95: begin outa = 10'h105; end
|
||||||
8'h96: begin outa = 10'h1ae; end
|
8'h96: begin outa = 10'h1ae; end
|
||||||
8'h97: begin outa = 10'h04e; end
|
8'h97: begin outa = 10'h04e; end
|
||||||
8'h98: begin outa = 10'h240; end
|
8'h98: begin outa = 10'h240; end
|
||||||
8'h99: begin outa = 10'h3e4; end
|
8'h99: begin outa = 10'h3e4; end
|
||||||
8'h9a: begin outa = 10'h3c6; end
|
8'h9a: begin outa = 10'h3c6; end
|
||||||
8'h9b: begin outa = 10'h109; end
|
8'h9b: begin outa = 10'h109; end
|
||||||
8'h9c: begin outa = 10'h073; end
|
8'h9c: begin outa = 10'h073; end
|
||||||
8'h9d: begin outa = 10'h19f; end
|
8'h9d: begin outa = 10'h19f; end
|
||||||
8'h9e: begin outa = 10'h3b8; end
|
8'h9e: begin outa = 10'h3b8; end
|
||||||
8'h9f: begin outa = 10'h00e; end
|
8'h9f: begin outa = 10'h00e; end
|
||||||
8'ha0: begin outa = 10'h1b3; end
|
8'ha0: begin outa = 10'h1b3; end
|
||||||
8'ha1: begin outa = 10'h2bd; end
|
8'ha1: begin outa = 10'h2bd; end
|
||||||
8'ha2: begin outa = 10'h324; end
|
8'ha2: begin outa = 10'h324; end
|
||||||
8'ha3: begin outa = 10'h343; end
|
8'ha3: begin outa = 10'h343; end
|
||||||
8'ha4: begin outa = 10'h1c9; end
|
8'ha4: begin outa = 10'h1c9; end
|
||||||
8'ha5: begin outa = 10'h185; end
|
8'ha5: begin outa = 10'h185; end
|
||||||
8'ha6: begin outa = 10'h37a; end
|
8'ha6: begin outa = 10'h37a; end
|
||||||
8'ha7: begin outa = 10'h0e0; end
|
8'ha7: begin outa = 10'h0e0; end
|
||||||
8'ha8: begin outa = 10'h0a3; end
|
8'ha8: begin outa = 10'h0a3; end
|
||||||
8'ha9: begin outa = 10'h019; end
|
8'ha9: begin outa = 10'h019; end
|
||||||
8'haa: begin outa = 10'h099; end
|
8'haa: begin outa = 10'h099; end
|
||||||
8'hab: begin outa = 10'h376; end
|
8'hab: begin outa = 10'h376; end
|
||||||
8'hac: begin outa = 10'h077; end
|
8'hac: begin outa = 10'h077; end
|
||||||
8'had: begin outa = 10'h2b1; end
|
8'had: begin outa = 10'h2b1; end
|
||||||
8'hae: begin outa = 10'h27f; end
|
8'hae: begin outa = 10'h27f; end
|
||||||
8'haf: begin outa = 10'h265; end
|
8'haf: begin outa = 10'h265; end
|
||||||
8'hb0: begin outa = 10'h156; end
|
8'hb0: begin outa = 10'h156; end
|
||||||
8'hb1: begin outa = 10'h1ce; end
|
8'hb1: begin outa = 10'h1ce; end
|
||||||
8'hb2: begin outa = 10'h008; end
|
8'hb2: begin outa = 10'h008; end
|
||||||
8'hb3: begin outa = 10'h12e; end
|
8'hb3: begin outa = 10'h12e; end
|
||||||
8'hb4: begin outa = 10'h199; end
|
8'hb4: begin outa = 10'h199; end
|
||||||
8'hb5: begin outa = 10'h330; end
|
8'hb5: begin outa = 10'h330; end
|
||||||
8'hb6: begin outa = 10'h1ab; end
|
8'hb6: begin outa = 10'h1ab; end
|
||||||
8'hb7: begin outa = 10'h3bd; end
|
8'hb7: begin outa = 10'h3bd; end
|
||||||
8'hb8: begin outa = 10'h0ca; end
|
8'hb8: begin outa = 10'h0ca; end
|
||||||
8'hb9: begin outa = 10'h367; end
|
8'hb9: begin outa = 10'h367; end
|
||||||
8'hba: begin outa = 10'h334; end
|
8'hba: begin outa = 10'h334; end
|
||||||
8'hbb: begin outa = 10'h040; end
|
8'hbb: begin outa = 10'h040; end
|
||||||
8'hbc: begin outa = 10'h1a7; end
|
8'hbc: begin outa = 10'h1a7; end
|
||||||
8'hbd: begin outa = 10'h036; end
|
8'hbd: begin outa = 10'h036; end
|
||||||
8'hbe: begin outa = 10'h223; end
|
8'hbe: begin outa = 10'h223; end
|
||||||
8'hbf: begin outa = 10'h075; end
|
8'hbf: begin outa = 10'h075; end
|
||||||
8'hc0: begin outa = 10'h3c4; end
|
8'hc0: begin outa = 10'h3c4; end
|
||||||
8'hc1: begin outa = 10'h2cc; end
|
8'hc1: begin outa = 10'h2cc; end
|
||||||
8'hc2: begin outa = 10'h123; end
|
8'hc2: begin outa = 10'h123; end
|
||||||
8'hc3: begin outa = 10'h3fd; end
|
8'hc3: begin outa = 10'h3fd; end
|
||||||
8'hc4: begin outa = 10'h11e; end
|
8'hc4: begin outa = 10'h11e; end
|
||||||
8'hc5: begin outa = 10'h27c; end
|
8'hc5: begin outa = 10'h27c; end
|
||||||
8'hc6: begin outa = 10'h1e2; end
|
8'hc6: begin outa = 10'h1e2; end
|
||||||
8'hc7: begin outa = 10'h377; end
|
8'hc7: begin outa = 10'h377; end
|
||||||
8'hc8: begin outa = 10'h33a; end
|
8'hc8: begin outa = 10'h33a; end
|
||||||
8'hc9: begin outa = 10'h32d; end
|
8'hc9: begin outa = 10'h32d; end
|
||||||
8'hca: begin outa = 10'h014; end
|
8'hca: begin outa = 10'h014; end
|
||||||
8'hcb: begin outa = 10'h332; end
|
8'hcb: begin outa = 10'h332; end
|
||||||
8'hcc: begin outa = 10'h359; end
|
8'hcc: begin outa = 10'h359; end
|
||||||
8'hcd: begin outa = 10'h0a4; end
|
8'hcd: begin outa = 10'h0a4; end
|
||||||
8'hce: begin outa = 10'h348; end
|
8'hce: begin outa = 10'h348; end
|
||||||
8'hcf: begin outa = 10'h04b; end
|
8'hcf: begin outa = 10'h04b; end
|
||||||
8'hd0: begin outa = 10'h147; end
|
8'hd0: begin outa = 10'h147; end
|
||||||
8'hd1: begin outa = 10'h026; end
|
8'hd1: begin outa = 10'h026; end
|
||||||
8'hd2: begin outa = 10'h103; end
|
8'hd2: begin outa = 10'h103; end
|
||||||
8'hd3: begin outa = 10'h106; end
|
8'hd3: begin outa = 10'h106; end
|
||||||
8'hd4: begin outa = 10'h35a; end
|
8'hd4: begin outa = 10'h35a; end
|
||||||
8'hd5: begin outa = 10'h254; end
|
8'hd5: begin outa = 10'h254; end
|
||||||
8'hd6: begin outa = 10'h0cd; end
|
8'hd6: begin outa = 10'h0cd; end
|
||||||
8'hd7: begin outa = 10'h17c; end
|
8'hd7: begin outa = 10'h17c; end
|
||||||
8'hd8: begin outa = 10'h37e; end
|
8'hd8: begin outa = 10'h37e; end
|
||||||
8'hd9: begin outa = 10'h0a9; end
|
8'hd9: begin outa = 10'h0a9; end
|
||||||
8'hda: begin outa = 10'h0fe; end
|
8'hda: begin outa = 10'h0fe; end
|
||||||
8'hdb: begin outa = 10'h3c0; end
|
8'hdb: begin outa = 10'h3c0; end
|
||||||
8'hdc: begin outa = 10'h1d9; end
|
8'hdc: begin outa = 10'h1d9; end
|
||||||
8'hdd: begin outa = 10'h10e; end
|
8'hdd: begin outa = 10'h10e; end
|
||||||
8'hde: begin outa = 10'h394; end
|
8'hde: begin outa = 10'h394; end
|
||||||
8'hdf: begin outa = 10'h316; end
|
8'hdf: begin outa = 10'h316; end
|
||||||
8'he0: begin outa = 10'h05b; end
|
8'he0: begin outa = 10'h05b; end
|
||||||
8'he1: begin outa = 10'h126; end
|
8'he1: begin outa = 10'h126; end
|
||||||
8'he2: begin outa = 10'h369; end
|
8'he2: begin outa = 10'h369; end
|
||||||
8'he3: begin outa = 10'h291; end
|
8'he3: begin outa = 10'h291; end
|
||||||
8'he4: begin outa = 10'h2ca; end
|
8'he4: begin outa = 10'h2ca; end
|
||||||
8'he5: begin outa = 10'h25b; end
|
8'he5: begin outa = 10'h25b; end
|
||||||
8'he6: begin outa = 10'h106; end
|
8'he6: begin outa = 10'h106; end
|
||||||
8'he7: begin outa = 10'h172; end
|
8'he7: begin outa = 10'h172; end
|
||||||
8'he8: begin outa = 10'h2f7; end
|
8'he8: begin outa = 10'h2f7; end
|
||||||
8'he9: begin outa = 10'h2d3; end
|
8'he9: begin outa = 10'h2d3; end
|
||||||
8'hea: begin outa = 10'h182; end
|
8'hea: begin outa = 10'h182; end
|
||||||
8'heb: begin outa = 10'h327; end
|
8'heb: begin outa = 10'h327; end
|
||||||
8'hec: begin outa = 10'h1d0; end
|
8'hec: begin outa = 10'h1d0; end
|
||||||
8'hed: begin outa = 10'h204; end
|
8'hed: begin outa = 10'h204; end
|
||||||
8'hee: begin outa = 10'h11f; end
|
8'hee: begin outa = 10'h11f; end
|
||||||
8'hef: begin outa = 10'h365; end
|
8'hef: begin outa = 10'h365; end
|
||||||
8'hf0: begin outa = 10'h2c2; end
|
8'hf0: begin outa = 10'h2c2; end
|
||||||
8'hf1: begin outa = 10'h2b5; end
|
8'hf1: begin outa = 10'h2b5; end
|
||||||
8'hf2: begin outa = 10'h1f8; end
|
8'hf2: begin outa = 10'h1f8; end
|
||||||
8'hf3: begin outa = 10'h2a7; end
|
8'hf3: begin outa = 10'h2a7; end
|
||||||
8'hf4: begin outa = 10'h1be; end
|
8'hf4: begin outa = 10'h1be; end
|
||||||
8'hf5: begin outa = 10'h25e; end
|
8'hf5: begin outa = 10'h25e; end
|
||||||
8'hf6: begin outa = 10'h032; end
|
8'hf6: begin outa = 10'h032; end
|
||||||
8'hf7: begin outa = 10'h2ef; end
|
8'hf7: begin outa = 10'h2ef; end
|
||||||
8'hf8: begin outa = 10'h02f; end
|
8'hf8: begin outa = 10'h02f; end
|
||||||
8'hf9: begin outa = 10'h201; end
|
8'hf9: begin outa = 10'h201; end
|
||||||
8'hfa: begin outa = 10'h054; end
|
8'hfa: begin outa = 10'h054; end
|
||||||
8'hfb: begin outa = 10'h013; end
|
8'hfb: begin outa = 10'h013; end
|
||||||
8'hfc: begin outa = 10'h249; end
|
8'hfc: begin outa = 10'h249; end
|
||||||
8'hfd: begin outa = 10'h09a; end
|
8'hfd: begin outa = 10'h09a; end
|
||||||
8'hfe: begin outa = 10'h012; end
|
8'hfe: begin outa = 10'h012; end
|
||||||
8'hff: begin outa = 10'h114; end
|
8'hff: begin outa = 10'h114; end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -18,7 +18,7 @@ module t_case_huge_sub3 (/*AUTOARG*/
|
||||||
// =============================
|
// =============================
|
||||||
/*AUTOREG*/
|
/*AUTOREG*/
|
||||||
// Beginning of automatic regs (for this module's undeclared outputs)
|
// Beginning of automatic regs (for this module's undeclared outputs)
|
||||||
reg [3:0] outr;
|
reg [3:0] outr;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
// =============================
|
// =============================
|
||||||
|
|
@ -31,262 +31,262 @@ module t_case_huge_sub3 (/*AUTOARG*/
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
case (index[7:0])
|
case (index[7:0])
|
||||||
8'h00: begin outr <= 4'h0; end
|
8'h00: begin outr <= 4'h0; end
|
||||||
8'h01: begin /*No Change*/ end
|
8'h01: begin /*No Change*/ end
|
||||||
8'h02: begin outr <= outr^index[8:5]^4'ha; end
|
8'h02: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h03: begin outr <= outr^index[8:5]^4'h4; end
|
8'h03: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h04: begin outr <= outr^index[8:5]^4'hd; end
|
8'h04: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'h05: begin outr <= outr^index[8:5]^4'h1; end
|
8'h05: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h06: begin outr <= outr^index[8:5]^4'hf; end
|
8'h06: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h07: begin outr <= outr^index[8:5]^4'he; end
|
8'h07: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'h08: begin outr <= outr^index[8:5]^4'h0; end
|
8'h08: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h09: begin outr <= outr^index[8:5]^4'h4; end
|
8'h09: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h0a: begin outr <= outr^index[8:5]^4'h5; end
|
8'h0a: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h0b: begin outr <= outr^index[8:5]^4'ha; end
|
8'h0b: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h0c: begin outr <= outr^index[8:5]^4'h2; end
|
8'h0c: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h0d: begin outr <= outr^index[8:5]^4'hf; end
|
8'h0d: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h0e: begin outr <= outr^index[8:5]^4'h5; end
|
8'h0e: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h0f: begin outr <= outr^index[8:5]^4'h0; end
|
8'h0f: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h10: begin outr <= outr^index[8:5]^4'h3; end
|
8'h10: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h11: begin outr <= outr^index[8:5]^4'hb; end
|
8'h11: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h12: begin outr <= outr^index[8:5]^4'h0; end
|
8'h12: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h13: begin outr <= outr^index[8:5]^4'hf; end
|
8'h13: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h14: begin outr <= outr^index[8:5]^4'h3; end
|
8'h14: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h15: begin outr <= outr^index[8:5]^4'h5; end
|
8'h15: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h16: begin outr <= outr^index[8:5]^4'h7; end
|
8'h16: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h17: begin outr <= outr^index[8:5]^4'h2; end
|
8'h17: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h18: begin outr <= outr^index[8:5]^4'h3; end
|
8'h18: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h19: begin outr <= outr^index[8:5]^4'hb; end
|
8'h19: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h1a: begin outr <= outr^index[8:5]^4'h5; end
|
8'h1a: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h1b: begin outr <= outr^index[8:5]^4'h4; end
|
8'h1b: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h1c: begin outr <= outr^index[8:5]^4'h2; end
|
8'h1c: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h1d: begin outr <= outr^index[8:5]^4'hf; end
|
8'h1d: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h1e: begin outr <= outr^index[8:5]^4'h0; end
|
8'h1e: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h1f: begin outr <= outr^index[8:5]^4'h4; end
|
8'h1f: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h20: begin outr <= outr^index[8:5]^4'h6; end
|
8'h20: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h21: begin outr <= outr^index[8:5]^4'ha; end
|
8'h21: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h22: begin outr <= outr^index[8:5]^4'h6; end
|
8'h22: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h23: begin outr <= outr^index[8:5]^4'hb; end
|
8'h23: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h24: begin outr <= outr^index[8:5]^4'ha; end
|
8'h24: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h25: begin outr <= outr^index[8:5]^4'he; end
|
8'h25: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'h26: begin outr <= outr^index[8:5]^4'h7; end
|
8'h26: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h27: begin outr <= outr^index[8:5]^4'ha; end
|
8'h27: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h28: begin outr <= outr^index[8:5]^4'h3; end
|
8'h28: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h29: begin outr <= outr^index[8:5]^4'h8; end
|
8'h29: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'h2a: begin outr <= outr^index[8:5]^4'h1; end
|
8'h2a: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h2b: begin outr <= outr^index[8:5]^4'h8; end
|
8'h2b: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'h2c: begin outr <= outr^index[8:5]^4'h4; end
|
8'h2c: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h2d: begin outr <= outr^index[8:5]^4'h4; end
|
8'h2d: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h2e: begin outr <= outr^index[8:5]^4'he; end
|
8'h2e: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'h2f: begin outr <= outr^index[8:5]^4'h8; end
|
8'h2f: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'h30: begin outr <= outr^index[8:5]^4'ha; end
|
8'h30: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h31: begin outr <= outr^index[8:5]^4'h7; end
|
8'h31: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h32: begin outr <= outr^index[8:5]^4'h0; end
|
8'h32: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h33: begin outr <= outr^index[8:5]^4'h3; end
|
8'h33: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h34: begin outr <= outr^index[8:5]^4'h1; end
|
8'h34: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h35: begin outr <= outr^index[8:5]^4'h3; end
|
8'h35: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h36: begin outr <= outr^index[8:5]^4'h4; end
|
8'h36: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h37: begin outr <= outr^index[8:5]^4'h6; end
|
8'h37: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h38: begin outr <= outr^index[8:5]^4'h4; end
|
8'h38: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h39: begin outr <= outr^index[8:5]^4'hb; end
|
8'h39: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h3a: begin outr <= outr^index[8:5]^4'h7; end
|
8'h3a: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h3b: begin outr <= outr^index[8:5]^4'h1; end
|
8'h3b: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h3c: begin outr <= outr^index[8:5]^4'h2; end
|
8'h3c: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h3d: begin outr <= outr^index[8:5]^4'h0; end
|
8'h3d: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h3e: begin outr <= outr^index[8:5]^4'h2; end
|
8'h3e: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h3f: begin outr <= outr^index[8:5]^4'ha; end
|
8'h3f: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h40: begin outr <= outr^index[8:5]^4'h7; end
|
8'h40: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h41: begin outr <= outr^index[8:5]^4'h5; end
|
8'h41: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h42: begin outr <= outr^index[8:5]^4'h5; end
|
8'h42: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h43: begin outr <= outr^index[8:5]^4'h4; end
|
8'h43: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h44: begin outr <= outr^index[8:5]^4'h8; end
|
8'h44: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'h45: begin outr <= outr^index[8:5]^4'h5; end
|
8'h45: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h46: begin outr <= outr^index[8:5]^4'hf; end
|
8'h46: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h47: begin outr <= outr^index[8:5]^4'h6; end
|
8'h47: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h48: begin outr <= outr^index[8:5]^4'h7; end
|
8'h48: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h49: begin outr <= outr^index[8:5]^4'h4; end
|
8'h49: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h4a: begin outr <= outr^index[8:5]^4'ha; end
|
8'h4a: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h4b: begin outr <= outr^index[8:5]^4'hd; end
|
8'h4b: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'h4c: begin outr <= outr^index[8:5]^4'hb; end
|
8'h4c: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h4d: begin outr <= outr^index[8:5]^4'hf; end
|
8'h4d: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h4e: begin outr <= outr^index[8:5]^4'hd; end
|
8'h4e: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'h4f: begin outr <= outr^index[8:5]^4'h7; end
|
8'h4f: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h50: begin outr <= outr^index[8:5]^4'h9; end
|
8'h50: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'h51: begin outr <= outr^index[8:5]^4'ha; end
|
8'h51: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h52: begin outr <= outr^index[8:5]^4'hf; end
|
8'h52: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h53: begin outr <= outr^index[8:5]^4'h3; end
|
8'h53: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h54: begin outr <= outr^index[8:5]^4'h1; end
|
8'h54: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h55: begin outr <= outr^index[8:5]^4'h0; end
|
8'h55: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h56: begin outr <= outr^index[8:5]^4'h2; end
|
8'h56: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h57: begin outr <= outr^index[8:5]^4'h9; end
|
8'h57: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'h58: begin outr <= outr^index[8:5]^4'h2; end
|
8'h58: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h59: begin outr <= outr^index[8:5]^4'h4; end
|
8'h59: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h5a: begin outr <= outr^index[8:5]^4'hc; end
|
8'h5a: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h5b: begin outr <= outr^index[8:5]^4'hd; end
|
8'h5b: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'h5c: begin outr <= outr^index[8:5]^4'h3; end
|
8'h5c: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h5d: begin outr <= outr^index[8:5]^4'hb; end
|
8'h5d: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h5e: begin outr <= outr^index[8:5]^4'hd; end
|
8'h5e: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'h5f: begin outr <= outr^index[8:5]^4'h7; end
|
8'h5f: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h60: begin outr <= outr^index[8:5]^4'h7; end
|
8'h60: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h61: begin outr <= outr^index[8:5]^4'h3; end
|
8'h61: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h62: begin outr <= outr^index[8:5]^4'h3; end
|
8'h62: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h63: begin outr <= outr^index[8:5]^4'hb; end
|
8'h63: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h64: begin outr <= outr^index[8:5]^4'h9; end
|
8'h64: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'h65: begin outr <= outr^index[8:5]^4'h4; end
|
8'h65: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h66: begin outr <= outr^index[8:5]^4'h3; end
|
8'h66: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h67: begin outr <= outr^index[8:5]^4'h6; end
|
8'h67: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h68: begin outr <= outr^index[8:5]^4'h7; end
|
8'h68: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h69: begin outr <= outr^index[8:5]^4'h7; end
|
8'h69: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h6a: begin outr <= outr^index[8:5]^4'hf; end
|
8'h6a: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h6b: begin outr <= outr^index[8:5]^4'h6; end
|
8'h6b: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h6c: begin outr <= outr^index[8:5]^4'h8; end
|
8'h6c: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'h6d: begin outr <= outr^index[8:5]^4'he; end
|
8'h6d: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'h6e: begin outr <= outr^index[8:5]^4'h4; end
|
8'h6e: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h6f: begin outr <= outr^index[8:5]^4'h6; end
|
8'h6f: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h70: begin outr <= outr^index[8:5]^4'hc; end
|
8'h70: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h71: begin outr <= outr^index[8:5]^4'h9; end
|
8'h71: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'h72: begin outr <= outr^index[8:5]^4'h5; end
|
8'h72: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h73: begin outr <= outr^index[8:5]^4'ha; end
|
8'h73: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h74: begin outr <= outr^index[8:5]^4'h7; end
|
8'h74: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h75: begin outr <= outr^index[8:5]^4'h0; end
|
8'h75: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h76: begin outr <= outr^index[8:5]^4'h1; end
|
8'h76: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h77: begin outr <= outr^index[8:5]^4'he; end
|
8'h77: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'h78: begin outr <= outr^index[8:5]^4'ha; end
|
8'h78: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h79: begin outr <= outr^index[8:5]^4'h7; end
|
8'h79: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h7a: begin outr <= outr^index[8:5]^4'hf; end
|
8'h7a: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'h7b: begin outr <= outr^index[8:5]^4'he; end
|
8'h7b: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'h7c: begin outr <= outr^index[8:5]^4'h6; end
|
8'h7c: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h7d: begin outr <= outr^index[8:5]^4'hc; end
|
8'h7d: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h7e: begin outr <= outr^index[8:5]^4'hc; end
|
8'h7e: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h7f: begin outr <= outr^index[8:5]^4'h0; end
|
8'h7f: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h80: begin outr <= outr^index[8:5]^4'h0; end
|
8'h80: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h81: begin outr <= outr^index[8:5]^4'hd; end
|
8'h81: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'h82: begin outr <= outr^index[8:5]^4'hb; end
|
8'h82: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h83: begin outr <= outr^index[8:5]^4'hc; end
|
8'h83: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h84: begin outr <= outr^index[8:5]^4'h2; end
|
8'h84: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h85: begin outr <= outr^index[8:5]^4'h8; end
|
8'h85: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'h86: begin outr <= outr^index[8:5]^4'h3; end
|
8'h86: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h87: begin outr <= outr^index[8:5]^4'ha; end
|
8'h87: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'h88: begin outr <= outr^index[8:5]^4'he; end
|
8'h88: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'h89: begin outr <= outr^index[8:5]^4'h9; end
|
8'h89: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'h8a: begin outr <= outr^index[8:5]^4'h1; end
|
8'h8a: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h8b: begin outr <= outr^index[8:5]^4'h1; end
|
8'h8b: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'h8c: begin outr <= outr^index[8:5]^4'hc; end
|
8'h8c: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h8d: begin outr <= outr^index[8:5]^4'h2; end
|
8'h8d: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h8e: begin outr <= outr^index[8:5]^4'h2; end
|
8'h8e: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'h8f: begin outr <= outr^index[8:5]^4'hd; end
|
8'h8f: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'h90: begin outr <= outr^index[8:5]^4'h0; end
|
8'h90: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h91: begin outr <= outr^index[8:5]^4'h6; end
|
8'h91: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h92: begin outr <= outr^index[8:5]^4'h7; end
|
8'h92: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h93: begin outr <= outr^index[8:5]^4'hc; end
|
8'h93: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h94: begin outr <= outr^index[8:5]^4'hb; end
|
8'h94: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h95: begin outr <= outr^index[8:5]^4'h3; end
|
8'h95: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'h96: begin outr <= outr^index[8:5]^4'h0; end
|
8'h96: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'h97: begin outr <= outr^index[8:5]^4'hc; end
|
8'h97: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h98: begin outr <= outr^index[8:5]^4'hc; end
|
8'h98: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'h99: begin outr <= outr^index[8:5]^4'hb; end
|
8'h99: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'h9a: begin outr <= outr^index[8:5]^4'h6; end
|
8'h9a: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'h9b: begin outr <= outr^index[8:5]^4'h5; end
|
8'h9b: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h9c: begin outr <= outr^index[8:5]^4'h5; end
|
8'h9c: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'h9d: begin outr <= outr^index[8:5]^4'h4; end
|
8'h9d: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'h9e: begin outr <= outr^index[8:5]^4'h7; end
|
8'h9e: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'h9f: begin outr <= outr^index[8:5]^4'he; end
|
8'h9f: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'ha0: begin outr <= outr^index[8:5]^4'hc; end
|
8'ha0: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'ha1: begin outr <= outr^index[8:5]^4'hc; end
|
8'ha1: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'ha2: begin outr <= outr^index[8:5]^4'h0; end
|
8'ha2: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'ha3: begin outr <= outr^index[8:5]^4'h1; end
|
8'ha3: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'ha4: begin outr <= outr^index[8:5]^4'hd; end
|
8'ha4: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'ha5: begin outr <= outr^index[8:5]^4'h3; end
|
8'ha5: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'ha6: begin outr <= outr^index[8:5]^4'hc; end
|
8'ha6: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'ha7: begin outr <= outr^index[8:5]^4'h2; end
|
8'ha7: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'ha8: begin outr <= outr^index[8:5]^4'h3; end
|
8'ha8: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'ha9: begin outr <= outr^index[8:5]^4'hd; end
|
8'ha9: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'haa: begin outr <= outr^index[8:5]^4'h5; end
|
8'haa: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'hab: begin outr <= outr^index[8:5]^4'hb; end
|
8'hab: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'hac: begin outr <= outr^index[8:5]^4'he; end
|
8'hac: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'had: begin outr <= outr^index[8:5]^4'h0; end
|
8'had: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'hae: begin outr <= outr^index[8:5]^4'hf; end
|
8'hae: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'haf: begin outr <= outr^index[8:5]^4'h9; end
|
8'haf: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'hb0: begin outr <= outr^index[8:5]^4'hf; end
|
8'hb0: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'hb1: begin outr <= outr^index[8:5]^4'h7; end
|
8'hb1: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'hb2: begin outr <= outr^index[8:5]^4'h9; end
|
8'hb2: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'hb3: begin outr <= outr^index[8:5]^4'hf; end
|
8'hb3: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'hb4: begin outr <= outr^index[8:5]^4'he; end
|
8'hb4: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hb5: begin outr <= outr^index[8:5]^4'h3; end
|
8'hb5: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'hb6: begin outr <= outr^index[8:5]^4'he; end
|
8'hb6: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hb7: begin outr <= outr^index[8:5]^4'h8; end
|
8'hb7: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'hb8: begin outr <= outr^index[8:5]^4'hf; end
|
8'hb8: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'hb9: begin outr <= outr^index[8:5]^4'hd; end
|
8'hb9: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'hba: begin outr <= outr^index[8:5]^4'h3; end
|
8'hba: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'hbb: begin outr <= outr^index[8:5]^4'h5; end
|
8'hbb: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'hbc: begin outr <= outr^index[8:5]^4'hd; end
|
8'hbc: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'hbd: begin outr <= outr^index[8:5]^4'ha; end
|
8'hbd: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'hbe: begin outr <= outr^index[8:5]^4'h7; end
|
8'hbe: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'hbf: begin outr <= outr^index[8:5]^4'he; end
|
8'hbf: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hc0: begin outr <= outr^index[8:5]^4'h2; end
|
8'hc0: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'hc1: begin outr <= outr^index[8:5]^4'he; end
|
8'hc1: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hc2: begin outr <= outr^index[8:5]^4'h9; end
|
8'hc2: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'hc3: begin outr <= outr^index[8:5]^4'hb; end
|
8'hc3: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'hc4: begin outr <= outr^index[8:5]^4'h0; end
|
8'hc4: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'hc5: begin outr <= outr^index[8:5]^4'h5; end
|
8'hc5: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'hc6: begin outr <= outr^index[8:5]^4'h9; end
|
8'hc6: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'hc7: begin outr <= outr^index[8:5]^4'h6; end
|
8'hc7: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'hc8: begin outr <= outr^index[8:5]^4'ha; end
|
8'hc8: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'hc9: begin outr <= outr^index[8:5]^4'hf; end
|
8'hc9: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'hca: begin outr <= outr^index[8:5]^4'h3; end
|
8'hca: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'hcb: begin outr <= outr^index[8:5]^4'hb; end
|
8'hcb: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'hcc: begin outr <= outr^index[8:5]^4'he; end
|
8'hcc: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hcd: begin outr <= outr^index[8:5]^4'h2; end
|
8'hcd: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'hce: begin outr <= outr^index[8:5]^4'h5; end
|
8'hce: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'hcf: begin outr <= outr^index[8:5]^4'hf; end
|
8'hcf: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'hd0: begin outr <= outr^index[8:5]^4'h2; end
|
8'hd0: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'hd1: begin outr <= outr^index[8:5]^4'h9; end
|
8'hd1: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'hd2: begin outr <= outr^index[8:5]^4'hb; end
|
8'hd2: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'hd3: begin outr <= outr^index[8:5]^4'h8; end
|
8'hd3: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'hd4: begin outr <= outr^index[8:5]^4'h0; end
|
8'hd4: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'hd5: begin outr <= outr^index[8:5]^4'h2; end
|
8'hd5: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'hd6: begin outr <= outr^index[8:5]^4'hb; end
|
8'hd6: begin outr <= outr^index[8:5]^4'hb; end
|
||||||
8'hd7: begin outr <= outr^index[8:5]^4'h2; end
|
8'hd7: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'hd8: begin outr <= outr^index[8:5]^4'ha; end
|
8'hd8: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'hd9: begin outr <= outr^index[8:5]^4'hf; end
|
8'hd9: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'hda: begin outr <= outr^index[8:5]^4'h8; end
|
8'hda: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'hdb: begin outr <= outr^index[8:5]^4'h4; end
|
8'hdb: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'hdc: begin outr <= outr^index[8:5]^4'he; end
|
8'hdc: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hdd: begin outr <= outr^index[8:5]^4'h6; end
|
8'hdd: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'hde: begin outr <= outr^index[8:5]^4'h9; end
|
8'hde: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'hdf: begin outr <= outr^index[8:5]^4'h9; end
|
8'hdf: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'he0: begin outr <= outr^index[8:5]^4'h7; end
|
8'he0: begin outr <= outr^index[8:5]^4'h7; end
|
||||||
8'he1: begin outr <= outr^index[8:5]^4'h0; end
|
8'he1: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'he2: begin outr <= outr^index[8:5]^4'h9; end
|
8'he2: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'he3: begin outr <= outr^index[8:5]^4'h3; end
|
8'he3: begin outr <= outr^index[8:5]^4'h3; end
|
||||||
8'he4: begin outr <= outr^index[8:5]^4'h2; end
|
8'he4: begin outr <= outr^index[8:5]^4'h2; end
|
||||||
8'he5: begin outr <= outr^index[8:5]^4'h4; end
|
8'he5: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'he6: begin outr <= outr^index[8:5]^4'h5; end
|
8'he6: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'he7: begin outr <= outr^index[8:5]^4'h5; end
|
8'he7: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'he8: begin outr <= outr^index[8:5]^4'hf; end
|
8'he8: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'he9: begin outr <= outr^index[8:5]^4'ha; end
|
8'he9: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'hea: begin outr <= outr^index[8:5]^4'hc; end
|
8'hea: begin outr <= outr^index[8:5]^4'hc; end
|
||||||
8'heb: begin outr <= outr^index[8:5]^4'hd; end
|
8'heb: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'hec: begin outr <= outr^index[8:5]^4'h1; end
|
8'hec: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'hed: begin outr <= outr^index[8:5]^4'h5; end
|
8'hed: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'hee: begin outr <= outr^index[8:5]^4'h9; end
|
8'hee: begin outr <= outr^index[8:5]^4'h9; end
|
||||||
8'hef: begin outr <= outr^index[8:5]^4'h0; end
|
8'hef: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'hf0: begin outr <= outr^index[8:5]^4'hd; end
|
8'hf0: begin outr <= outr^index[8:5]^4'hd; end
|
||||||
8'hf1: begin outr <= outr^index[8:5]^4'hf; end
|
8'hf1: begin outr <= outr^index[8:5]^4'hf; end
|
||||||
8'hf2: begin outr <= outr^index[8:5]^4'h4; end
|
8'hf2: begin outr <= outr^index[8:5]^4'h4; end
|
||||||
8'hf3: begin outr <= outr^index[8:5]^4'ha; end
|
8'hf3: begin outr <= outr^index[8:5]^4'ha; end
|
||||||
8'hf4: begin outr <= outr^index[8:5]^4'h8; end
|
8'hf4: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'hf5: begin outr <= outr^index[8:5]^4'he; end
|
8'hf5: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hf6: begin outr <= outr^index[8:5]^4'he; end
|
8'hf6: begin outr <= outr^index[8:5]^4'he; end
|
||||||
8'hf7: begin outr <= outr^index[8:5]^4'h1; end
|
8'hf7: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'hf8: begin outr <= outr^index[8:5]^4'h6; end
|
8'hf8: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'hf9: begin outr <= outr^index[8:5]^4'h0; end
|
8'hf9: begin outr <= outr^index[8:5]^4'h0; end
|
||||||
8'hfa: begin outr <= outr^index[8:5]^4'h5; end
|
8'hfa: begin outr <= outr^index[8:5]^4'h5; end
|
||||||
8'hfb: begin outr <= outr^index[8:5]^4'h1; end
|
8'hfb: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
8'hfc: begin outr <= outr^index[8:5]^4'h8; end
|
8'hfc: begin outr <= outr^index[8:5]^4'h8; end
|
||||||
8'hfd: begin outr <= outr^index[8:5]^4'h6; end
|
8'hfd: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
8'hfe: begin outr <= outr^index[8:5]^4'h1; end
|
8'hfe: begin outr <= outr^index[8:5]^4'h1; end
|
||||||
default: begin outr <= outr^index[8:5]^4'h6; end
|
default: begin outr <= outr^index[8:5]^4'h6; end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -19,47 +19,47 @@ module t_case_huge_sub4 (/*AUTOARG*/
|
||||||
// =============================
|
// =============================
|
||||||
/*AUTOREG*/
|
/*AUTOREG*/
|
||||||
// Beginning of automatic regs (for this module's undeclared outputs)
|
// Beginning of automatic regs (for this module's undeclared outputs)
|
||||||
reg [9:0] outq;
|
reg [9:0] outq;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
// =============================
|
// =============================
|
||||||
always @(/*AS*/index) begin
|
always @(/*AS*/index) begin
|
||||||
case (index)
|
case (index)
|
||||||
// default below: no change
|
// default below: no change
|
||||||
8'h00: begin outq = 10'h001; end
|
8'h00: begin outq = 10'h001; end
|
||||||
8'he0: begin outq = 10'h05b; end
|
8'he0: begin outq = 10'h05b; end
|
||||||
8'he1: begin outq = 10'h126; end
|
8'he1: begin outq = 10'h126; end
|
||||||
8'he2: begin outq = 10'h369; end
|
8'he2: begin outq = 10'h369; end
|
||||||
8'he3: begin outq = 10'h291; end
|
8'he3: begin outq = 10'h291; end
|
||||||
8'he4: begin outq = 10'h2ca; end
|
8'he4: begin outq = 10'h2ca; end
|
||||||
8'he5: begin outq = 10'h25b; end
|
8'he5: begin outq = 10'h25b; end
|
||||||
8'he6: begin outq = 10'h106; end
|
8'he6: begin outq = 10'h106; end
|
||||||
8'he7: begin outq = 10'h172; end
|
8'he7: begin outq = 10'h172; end
|
||||||
8'he8: begin outq = 10'h2f7; end
|
8'he8: begin outq = 10'h2f7; end
|
||||||
8'he9: begin outq = 10'h2d3; end
|
8'he9: begin outq = 10'h2d3; end
|
||||||
8'hea: begin outq = 10'h182; end
|
8'hea: begin outq = 10'h182; end
|
||||||
8'heb: begin outq = 10'h327; end
|
8'heb: begin outq = 10'h327; end
|
||||||
8'hec: begin outq = 10'h1d0; end
|
8'hec: begin outq = 10'h1d0; end
|
||||||
8'hed: begin outq = 10'h204; end
|
8'hed: begin outq = 10'h204; end
|
||||||
8'hee: begin outq = 10'h11f; end
|
8'hee: begin outq = 10'h11f; end
|
||||||
8'hef: begin outq = 10'h365; end
|
8'hef: begin outq = 10'h365; end
|
||||||
8'hf0: begin outq = 10'h2c2; end
|
8'hf0: begin outq = 10'h2c2; end
|
||||||
8'hf1: begin outq = 10'h2b5; end
|
8'hf1: begin outq = 10'h2b5; end
|
||||||
8'hf2: begin outq = 10'h1f8; end
|
8'hf2: begin outq = 10'h1f8; end
|
||||||
8'hf3: begin outq = 10'h2a7; end
|
8'hf3: begin outq = 10'h2a7; end
|
||||||
8'hf4: begin outq = 10'h1be; end
|
8'hf4: begin outq = 10'h1be; end
|
||||||
8'hf5: begin outq = 10'h25e; end
|
8'hf5: begin outq = 10'h25e; end
|
||||||
8'hf6: begin outq = 10'h032; end
|
8'hf6: begin outq = 10'h032; end
|
||||||
8'hf7: begin outq = 10'h2ef; end
|
8'hf7: begin outq = 10'h2ef; end
|
||||||
8'hf8: begin outq = 10'h02f; end
|
8'hf8: begin outq = 10'h02f; end
|
||||||
8'hf9: begin outq = 10'h201; end
|
8'hf9: begin outq = 10'h201; end
|
||||||
8'hfa: begin outq = 10'h054; end
|
8'hfa: begin outq = 10'h054; end
|
||||||
8'hfb: begin outq = 10'h013; end
|
8'hfb: begin outq = 10'h013; end
|
||||||
8'hfc: begin outq = 10'h249; end
|
8'hfc: begin outq = 10'h249; end
|
||||||
8'hfd: begin outq = 10'h09a; end
|
8'hfd: begin outq = 10'h09a; end
|
||||||
8'hfe: begin outq = 10'h012; end
|
8'hfe: begin outq = 10'h012; end
|
||||||
8'hff: begin outq = 10'h114; end
|
8'hff: begin outq = 10'h114; end
|
||||||
default: ; // No change
|
default: ; // No change
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -15,7 +15,7 @@ module t (/*AUTOARG*/
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
reg out1;
|
reg out1;
|
||||||
reg [4:0] out2;
|
reg [4:0] out2;
|
||||||
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
|
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
|
||||||
|
|
||||||
|
|
@ -27,16 +27,16 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
|
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h00000000_00000097;
|
crc <= 64'h00000000_00000097;
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
`define EXPECTED_SUM 64'h10204fa5567c8a4b
|
`define EXPECTED_SUM 64'h10204fa5567c8a4b
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -50,17 +50,17 @@ module sub (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
|
|
||||||
input [23:0] in;
|
input [23:0] in;
|
||||||
output reg out1;
|
output reg out1;
|
||||||
output reg [4:0] out2;
|
output reg [4:0] out2;
|
||||||
|
|
||||||
always @* begin
|
always @* begin
|
||||||
case (in[3:0]) inside
|
case (in[3:0]) inside
|
||||||
default: {out1,out2} = {1'b0,5'h0F}; // Note not last item
|
default: {out1,out2} = {1'b0,5'h0F}; // Note not last item
|
||||||
4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
|
4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
|
||||||
4'h4: {out1,out2} = {1'b1,5'h04};
|
4'h4: {out1,out2} = {1'b1,5'h04};
|
||||||
[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
|
[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
|
||||||
4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
|
4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
|
||||||
[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
|
[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -22,66 +22,66 @@ module t (/*AUTOARG*/
|
||||||
reg [2:0] wrapcheck_b;
|
reg [2:0] wrapcheck_b;
|
||||||
|
|
||||||
test test (/*AUTOINST*/
|
test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.data (data[7:0]),
|
.data (data[7:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.addr (addr[6:0]),
|
.addr (addr[6:0]),
|
||||||
.e0 (e0[6:0]),
|
.e0 (e0[6:0]),
|
||||||
.e1 (e1[5:0]),
|
.e1 (e1[5:0]),
|
||||||
.e2 (e2[5:0]));
|
.e2 (e2[5:0]));
|
||||||
|
|
||||||
always @(/*AS*/addr) begin
|
always @(/*AS*/addr) begin
|
||||||
case(addr[2:0])
|
case(addr[2:0])
|
||||||
3'd0+3'd0: wrapcheck_a = 3'h0;
|
3'd0+3'd0: wrapcheck_a = 3'h0;
|
||||||
3'd0+3'd1: wrapcheck_a = 3'h1;
|
3'd0+3'd1: wrapcheck_a = 3'h1;
|
||||||
3'd0+3'd2: wrapcheck_a = 3'h2;
|
3'd0+3'd2: wrapcheck_a = 3'h2;
|
||||||
3'd0+3'd3: wrapcheck_a = 3'h3;
|
3'd0+3'd3: wrapcheck_a = 3'h3;
|
||||||
default: wrapcheck_a = 3'h4;
|
default: wrapcheck_a = 3'h4;
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
case(addr[2:0])
|
case(addr[2:0])
|
||||||
3'd0+0: wrapcheck_b = 3'h0;
|
3'd0+0: wrapcheck_b = 3'h0;
|
||||||
3'd1+1: wrapcheck_b = 3'h1;
|
3'd1+1: wrapcheck_b = 3'h1;
|
||||||
3'd2+2: wrapcheck_b = 3'h2;
|
3'd2+2: wrapcheck_b = 3'h2;
|
||||||
3'd3+3: wrapcheck_b = 3'h3;
|
3'd3+3: wrapcheck_b = 3'h3;
|
||||||
default: wrapcheck_b = 3'h4;
|
default: wrapcheck_b = 3'h4;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
|
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
addr <= 7'h28;
|
addr <= 7'h28;
|
||||||
e0 <= 7'h11;
|
e0 <= 7'h11;
|
||||||
e1 <= 6'h02;
|
e1 <= 6'h02;
|
||||||
e2 <= 6'h03;
|
e2 <= 6'h03;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
addr <= 7'h2b;
|
addr <= 7'h2b;
|
||||||
if (data != 8'h11) $stop;
|
if (data != 8'h11) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
addr <= 7'h2c;
|
addr <= 7'h2c;
|
||||||
if (data != 8'h03) $stop;
|
if (data != 8'h03) $stop;
|
||||||
if (wrapcheck_a != 3'h3) $stop;
|
if (wrapcheck_a != 3'h3) $stop;
|
||||||
if (wrapcheck_b != 3'h4) $stop;
|
if (wrapcheck_b != 3'h4) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
addr <= 7'h0;
|
addr <= 7'h0;
|
||||||
if (data != 8'h00) $stop;
|
if (data != 8'h00) $stop;
|
||||||
if (wrapcheck_a != 3'h4) $stop;
|
if (wrapcheck_a != 3'h4) $stop;
|
||||||
if (wrapcheck_b != 3'h2) $stop;
|
if (wrapcheck_b != 3'h2) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==5) begin
|
if (cyc==5) begin
|
||||||
if (data != 8'h00) $stop;
|
if (data != 8'h00) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -97,23 +97,23 @@ module test (/*AUTOARG*/
|
||||||
addr, e0, e1, e2
|
addr, e0, e1, e2
|
||||||
);
|
);
|
||||||
|
|
||||||
output [7:0] data;
|
output [7:0] data;
|
||||||
|
|
||||||
input [6:0] addr;
|
input [6:0] addr;
|
||||||
input [6:0] e0;
|
input [6:0] e0;
|
||||||
input [5:0] e1, e2;
|
input [5:0] e1, e2;
|
||||||
|
|
||||||
reg [7:0] data;
|
reg [7:0] data;
|
||||||
|
|
||||||
always @(/*AS*/addr or e0 or e1 or e2)
|
always @(/*AS*/addr or e0 or e1 or e2)
|
||||||
begin
|
begin
|
||||||
case (addr)
|
case (addr)
|
||||||
`AI: data = {e0[6], 1'b0, e0[5:0]};
|
`AI: data = {e0[6], 1'b0, e0[5:0]};
|
||||||
`AI+1: data = e1;
|
`AI+1: data = e1;
|
||||||
`AI+2,
|
`AI+2,
|
||||||
`AI+3: data = e2;
|
`AI+3: data = e2;
|
||||||
default: data = 0;
|
default: data = 0;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -15,7 +15,7 @@ module t (/*AUTOARG*/
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
reg out1;
|
reg out1;
|
||||||
sub sub (.in(crc[23:0]), .out1(out1));
|
sub sub (.in(crc[23:0]), .out1(out1));
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
|
|
@ -26,12 +26,12 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
|
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h00000000_00000097;
|
crc <= 64'h00000000_00000097;
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc==90) begin
|
else if (cyc==90) begin
|
||||||
if (sum !== 64'h2e5cb972eb02b8a0) $stop;
|
if (sum !== 64'h2e5cb972eb02b8a0) $stop;
|
||||||
end
|
end
|
||||||
else if (cyc==91) begin
|
else if (cyc==91) begin
|
||||||
end
|
end
|
||||||
|
|
@ -42,8 +42,8 @@ module t (/*AUTOARG*/
|
||||||
else if (cyc==94) begin
|
else if (cyc==94) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -63,48 +63,48 @@ module sub (/*AUTOARG*/
|
||||||
|
|
||||||
always @* begin
|
always @* begin
|
||||||
casez (in[17:16])
|
casez (in[17:16])
|
||||||
2'b00: casez (in[2:0])
|
2'b00: casez (in[2:0])
|
||||||
3'h0: out1[0] = in[0]^RANDOM[0];
|
3'h0: out1[0] = in[0]^RANDOM[0];
|
||||||
3'h1: out1[0] = in[0]^RANDOM[1];
|
3'h1: out1[0] = in[0]^RANDOM[1];
|
||||||
3'h2: out1[0] = in[0]^RANDOM[2];
|
3'h2: out1[0] = in[0]^RANDOM[2];
|
||||||
3'h3: out1[0] = in[0]^RANDOM[3];
|
3'h3: out1[0] = in[0]^RANDOM[3];
|
||||||
3'h4: out1[0] = in[0]^RANDOM[4];
|
3'h4: out1[0] = in[0]^RANDOM[4];
|
||||||
3'h5: out1[0] = in[0]^RANDOM[5];
|
3'h5: out1[0] = in[0]^RANDOM[5];
|
||||||
3'h6: out1[0] = in[0]^RANDOM[6];
|
3'h6: out1[0] = in[0]^RANDOM[6];
|
||||||
3'h7: out1[0] = in[0]^RANDOM[7];
|
3'h7: out1[0] = in[0]^RANDOM[7];
|
||||||
endcase
|
endcase
|
||||||
2'b01: casez (in[2:0])
|
2'b01: casez (in[2:0])
|
||||||
3'h0: out1[0] = RANDOM[10];
|
3'h0: out1[0] = RANDOM[10];
|
||||||
3'h1: out1[0] = RANDOM[11];
|
3'h1: out1[0] = RANDOM[11];
|
||||||
3'h2: out1[0] = RANDOM[12];
|
3'h2: out1[0] = RANDOM[12];
|
||||||
3'h3: out1[0] = RANDOM[13];
|
3'h3: out1[0] = RANDOM[13];
|
||||||
3'h4: out1[0] = RANDOM[14];
|
3'h4: out1[0] = RANDOM[14];
|
||||||
3'h5: out1[0] = RANDOM[15];
|
3'h5: out1[0] = RANDOM[15];
|
||||||
3'h6: out1[0] = RANDOM[16];
|
3'h6: out1[0] = RANDOM[16];
|
||||||
3'h7: out1[0] = RANDOM[17];
|
3'h7: out1[0] = RANDOM[17];
|
||||||
endcase
|
endcase
|
||||||
2'b1?: casez (in[4])
|
2'b1?: casez (in[4])
|
||||||
1'b1: casez (in[2:0])
|
1'b1: casez (in[2:0])
|
||||||
3'h0: out1[0] = RANDOM[20];
|
3'h0: out1[0] = RANDOM[20];
|
||||||
3'h1: out1[0] = RANDOM[21];
|
3'h1: out1[0] = RANDOM[21];
|
||||||
3'h2: out1[0] = RANDOM[22];
|
3'h2: out1[0] = RANDOM[22];
|
||||||
3'h3: out1[0] = RANDOM[23];
|
3'h3: out1[0] = RANDOM[23];
|
||||||
3'h4: out1[0] = RANDOM[24];
|
3'h4: out1[0] = RANDOM[24];
|
||||||
3'h5: out1[0] = RANDOM[25];
|
3'h5: out1[0] = RANDOM[25];
|
||||||
3'h6: out1[0] = RANDOM[26];
|
3'h6: out1[0] = RANDOM[26];
|
||||||
3'h7: out1[0] = RANDOM[27];
|
3'h7: out1[0] = RANDOM[27];
|
||||||
endcase
|
endcase
|
||||||
1'b0: casez (in[2:0])
|
1'b0: casez (in[2:0])
|
||||||
3'h0: out1[0] = RANDOM[30];
|
3'h0: out1[0] = RANDOM[30];
|
||||||
3'h1: out1[0] = RANDOM[31];
|
3'h1: out1[0] = RANDOM[31];
|
||||||
3'h2: out1[0] = RANDOM[32];
|
3'h2: out1[0] = RANDOM[32];
|
||||||
3'h3: out1[0] = RANDOM[33];
|
3'h3: out1[0] = RANDOM[33];
|
||||||
3'h4: out1[0] = RANDOM[34];
|
3'h4: out1[0] = RANDOM[34];
|
||||||
3'h5: out1[0] = RANDOM[35];
|
3'h5: out1[0] = RANDOM[35];
|
||||||
3'h6: out1[0] = RANDOM[36];
|
3'h6: out1[0] = RANDOM[36];
|
||||||
3'h7: out1[0] = RANDOM[37];
|
3'h7: out1[0] = RANDOM[37];
|
||||||
endcase
|
endcase
|
||||||
endcase
|
endcase
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,26 +10,26 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire [2:0] in = (crc[1:0]==0 ? 3'd0
|
wire [2:0] in = (crc[1:0]==0 ? 3'd0
|
||||||
: crc[1:0]==0 ? 3'd1
|
: crc[1:0]==0 ? 3'd1
|
||||||
: crc[1:0]==0 ? 3'd2 : 3'd4);
|
: crc[1:0]==0 ? 3'd2 : 3'd4);
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [31:0] out; // From test of Test.v
|
wire [31:0] out; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out (out[31:0]),
|
.out (out[31:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.in (in[2:0]));
|
.in (in[2:0]));
|
||||||
|
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
wire [63:0] result = {32'h0, out};
|
wire [63:0] result = {32'h0, out};
|
||||||
|
|
@ -43,23 +43,23 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
// What checksum will we end up with (above print should match)
|
// What checksum will we end up with (above print should match)
|
||||||
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
|
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -87,10 +87,10 @@ module Test (/*AUTOARG*/
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
case (1'b1) // synopsys parallel_case
|
case (1'b1) // synopsys parallel_case
|
||||||
in[ST_0]: out <= 32'h1234;
|
in[ST_0]: out <= 32'h1234;
|
||||||
in[ST_1]: out <= 32'h4356;
|
in[ST_1]: out <= 32'h4356;
|
||||||
in[ST_2]: out <= 32'h9874;
|
in[ST_2]: out <= 32'h9874;
|
||||||
default: out <= 32'h1;
|
default: out <= 32'h1;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -10,9 +10,9 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
reg _ranit;
|
reg _ranit;
|
||||||
|
|
||||||
reg rnd;
|
reg rnd;
|
||||||
reg [2:0] a;
|
reg [2:0] a;
|
||||||
reg [2:0] b;
|
reg [2:0] b;
|
||||||
reg [31:0] wide;
|
reg [31:0] wide;
|
||||||
|
|
@ -22,108 +22,108 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
wire sigone1 = 1'b1;
|
wire sigone1 = 1'b1;
|
||||||
wire sigone2 = 1'b1;
|
wire sigone2 = 1'b1;
|
||||||
reg ok;
|
reg ok;
|
||||||
|
|
||||||
parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b??
|
parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b??
|
||||||
|
|
||||||
// Large case statements should be well optimizable.
|
// Large case statements should be well optimizable.
|
||||||
reg [2:0] anot;
|
reg [2:0] anot;
|
||||||
always @ (/*AS*/a) begin
|
always @ (/*AS*/a) begin
|
||||||
casez (a)
|
casez (a)
|
||||||
default: anot = 3'b001;
|
default: anot = 3'b001;
|
||||||
3'd0: anot = 3'b111;
|
3'd0: anot = 3'b111;
|
||||||
3'd1: anot = 3'b110;
|
3'd1: anot = 3'b110;
|
||||||
3'd2: anot = 3'b101;
|
3'd2: anot = 3'b101;
|
||||||
3'd3: anot = 3'b101;
|
3'd3: anot = 3'b101;
|
||||||
3'd4: anot = 3'b011;
|
3'd4: anot = 3'b011;
|
||||||
3'd5: anot = 3'b010;
|
3'd5: anot = 3'b010;
|
||||||
3'd6: anot = 3'b001; // Same so folds with 7
|
3'd6: anot = 3'b001; // Same so folds with 7
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (!_ranit) begin
|
if (!_ranit) begin
|
||||||
_ranit <= 1;
|
_ranit <= 1;
|
||||||
rnd <= 1;
|
rnd <= 1;
|
||||||
$write("[%0t] t_case: Running\n", $time);
|
$write("[%0t] t_case: Running\n", $time);
|
||||||
//
|
//
|
||||||
a = 3'b101;
|
a = 3'b101;
|
||||||
b = 3'b111;
|
b = 3'b111;
|
||||||
// verilator lint_off CASEX
|
// verilator lint_off CASEX
|
||||||
casex (a)
|
casex (a)
|
||||||
default: $stop;
|
default: $stop;
|
||||||
3'bx1x: $stop;
|
3'bx1x: $stop;
|
||||||
3'b100: $stop;
|
3'b100: $stop;
|
||||||
3'bx01: ;
|
3'bx01: ;
|
||||||
endcase
|
endcase
|
||||||
casez (a)
|
casez (a)
|
||||||
default: $stop;
|
default: $stop;
|
||||||
3'b?1?: $stop;
|
3'b?1?: $stop;
|
||||||
3'b100: $stop;
|
3'b100: $stop;
|
||||||
3'b?01: ;
|
3'b?01: ;
|
||||||
endcase
|
endcase
|
||||||
casez (a)
|
casez (a)
|
||||||
default: $stop;
|
default: $stop;
|
||||||
{1'b0, twounkn}: $stop;
|
{1'b0, twounkn}: $stop;
|
||||||
{1'b1, twounkn}: ;
|
{1'b1, twounkn}: ;
|
||||||
endcase
|
endcase
|
||||||
casez (b)
|
casez (b)
|
||||||
default: $stop;
|
default: $stop;
|
||||||
{1'b0, twounkn}: $stop;
|
{1'b0, twounkn}: $stop;
|
||||||
{1'b1, twounkn}: ;
|
{1'b1, twounkn}: ;
|
||||||
// {1'b0, 2'b??}: $stop;
|
// {1'b0, 2'b??}: $stop;
|
||||||
// {1'b1, 2'b??}: ;
|
// {1'b1, 2'b??}: ;
|
||||||
endcase
|
endcase
|
||||||
case(a[0])
|
case(a[0])
|
||||||
default: ;
|
default: ;
|
||||||
endcase
|
endcase
|
||||||
casex(a)
|
casex(a)
|
||||||
default: ;
|
default: ;
|
||||||
3'b?0?: ;
|
3'b?0?: ;
|
||||||
endcase
|
endcase
|
||||||
// verilator lint_off CASEX
|
// verilator lint_off CASEX
|
||||||
//This is illegal, the default occurs before the statements.
|
//This is illegal, the default occurs before the statements.
|
||||||
//case(a[0])
|
//case(a[0])
|
||||||
// default: $stop;
|
// default: $stop;
|
||||||
// 1'b1: ;
|
// 1'b1: ;
|
||||||
//endcase
|
//endcase
|
||||||
//
|
//
|
||||||
wide = 32'h12345678;
|
wide = 32'h12345678;
|
||||||
casez (wide)
|
casez (wide)
|
||||||
default: $stop;
|
default: $stop;
|
||||||
32'h12345677,
|
32'h12345677,
|
||||||
32'h12345678,
|
32'h12345678,
|
||||||
32'h12345679: ;
|
32'h12345679: ;
|
||||||
endcase
|
endcase
|
||||||
//
|
//
|
||||||
ok = 0;
|
ok = 0;
|
||||||
casez ({sigone1,sigone2})
|
casez ({sigone1,sigone2})
|
||||||
//2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true...
|
//2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true...
|
||||||
2'b10, 2'b01: ;
|
2'b10, 2'b01: ;
|
||||||
2'b00: ;
|
2'b00: ;
|
||||||
default: ok=1'b1;
|
default: ok=1'b1;
|
||||||
endcase
|
endcase
|
||||||
if (ok !== 1'b1) $stop;
|
if (ok !== 1'b1) $stop;
|
||||||
//
|
//
|
||||||
|
|
||||||
if (rnd) begin
|
if (rnd) begin
|
||||||
$write("");
|
$write("");
|
||||||
end
|
end
|
||||||
//
|
//
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// Check parameters in case statements
|
// Check parameters in case statements
|
||||||
parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr.
|
parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr.
|
||||||
parameter DSP_REGISTER_V = 6'h03;
|
parameter DSP_REGISTER_V = 6'h03;
|
||||||
|
|
||||||
reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl
|
reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl
|
||||||
reg [5:0] reg_addr_2s; // Delayed version of reg_addr
|
reg [5:0] reg_addr_2s; // Delayed version of reg_addr
|
||||||
reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases
|
reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases
|
||||||
reg [15:10] f_tmp_2s; // Delayed copy of F
|
reg [15:10] f_tmp_2s; // Delayed copy of F
|
||||||
reg p00_2s;
|
reg p00_2s;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
alu_ctl_2s = 3'h1;
|
alu_ctl_2s = 3'h1;
|
||||||
|
|
@ -131,16 +131,16 @@ module t (/*AUTOARG*/
|
||||||
ir_slave_2s= 0;
|
ir_slave_2s= 0;
|
||||||
f_tmp_2s= 0;
|
f_tmp_2s= 0;
|
||||||
casex ({alu_ctl_2s,reg_addr_2s,
|
casex ({alu_ctl_2s,reg_addr_2s,
|
||||||
ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0],
|
ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0],
|
||||||
f_tmp_2s[11:10]})
|
f_tmp_2s[11:10]})
|
||||||
default: p00_2s = 1'b0;
|
default: p00_2s = 1'b0;
|
||||||
{ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1;
|
{ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1;
|
||||||
endcase
|
endcase
|
||||||
if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused
|
if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused
|
||||||
//
|
//
|
||||||
case ({1'b1, 1'b1})
|
case ({1'b1, 1'b1})
|
||||||
default: $stop;
|
default: $stop;
|
||||||
{1'b1, p00_2s}: ;
|
{1'b1, p00_2s}: ;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -151,24 +151,24 @@ module t (/*AUTOARG*/
|
||||||
initial begin
|
initial begin
|
||||||
foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0};
|
foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0};
|
||||||
casez (foo)
|
casez (foo)
|
||||||
default: $stop;
|
default: $stop;
|
||||||
{1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop;
|
{1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop;
|
||||||
{1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop;
|
{1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop;
|
||||||
{1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop;
|
{1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop;
|
||||||
{1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop;
|
{1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop;
|
||||||
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ;
|
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ;
|
||||||
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop;
|
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop;
|
||||||
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop;
|
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
initial begin
|
initial begin
|
||||||
foo = 20'b1010;
|
foo = 20'b1010;
|
||||||
casex (foo[3:0])
|
casex (foo[3:0])
|
||||||
default: $stop;
|
default: $stop;
|
||||||
4'b0xxx,
|
4'b0xxx,
|
||||||
4'b100x,
|
4'b100x,
|
||||||
4'b11xx: $stop;
|
4'b11xx: $stop;
|
||||||
4'b1010: ;
|
4'b1010: ;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
initial begin
|
initial begin
|
||||||
|
|
@ -176,10 +176,10 @@ module t (/*AUTOARG*/
|
||||||
ok = 1'b0;
|
ok = 1'b0;
|
||||||
// Test of RANGE(CONCAT reductions...
|
// Test of RANGE(CONCAT reductions...
|
||||||
casex ({foo[3:2],foo[1:0],foo[3]})
|
casex ({foo[3:2],foo[1:0],foo[3]})
|
||||||
5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions
|
5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions
|
||||||
5'bxx00x: $stop;
|
5'bxx00x: $stop;
|
||||||
5'bxx01x: $stop;
|
5'bxx01x: $stop;
|
||||||
5'bxx11x: $stop;
|
5'bxx11x: $stop;
|
||||||
endcase
|
endcase
|
||||||
if (!ok) $stop;
|
if (!ok) $stop;
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -10,9 +10,9 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire [7:0] operand_a = crc[7:0];
|
wire [7:0] operand_a = crc[7:0];
|
||||||
|
|
@ -20,16 +20,16 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [6:0] out; // From test of Test.v
|
wire [6:0] out; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out (out[6:0]),
|
.out (out[6:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.operand_a (operand_a[7:0]),
|
.operand_a (operand_a[7:0]),
|
||||||
.operand_b (operand_b[7:0]));
|
.operand_b (operand_b[7:0]));
|
||||||
|
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
wire [63:0] result = {57'h0, out};
|
wire [63:0] result = {57'h0, out};
|
||||||
|
|
@ -43,23 +43,23 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
// What checksum will we end up with (above print should match)
|
// What checksum will we end up with (above print should match)
|
||||||
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
|
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -68,15 +68,15 @@ endmodule
|
||||||
module Test
|
module Test
|
||||||
(
|
(
|
||||||
// Inputs
|
// Inputs
|
||||||
input wire clk,
|
input wire clk,
|
||||||
input wire [7:0] operand_a, // operand a
|
input wire [7:0] operand_a, // operand a
|
||||||
input wire [7:0] operand_b, // operand b
|
input wire [7:0] operand_b, // operand b
|
||||||
// Outputs
|
// Outputs
|
||||||
output wire [6:0] out
|
output wire [6:0] out
|
||||||
);
|
);
|
||||||
|
|
||||||
wire [6:0] clz_a;
|
wire [6:0] clz_a;
|
||||||
wire [6:0] clz_b;
|
wire [6:0] clz_b;
|
||||||
|
|
||||||
clz u_clz_a
|
clz u_clz_a
|
||||||
(
|
(
|
||||||
|
|
|
||||||
|
|
@ -15,7 +15,7 @@ module t (/*AUTOARG*/
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
reg out1;
|
reg out1;
|
||||||
reg [4:0] out2;
|
reg [4:0] out2;
|
||||||
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
|
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
|
||||||
|
|
||||||
|
|
@ -25,12 +25,12 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
|
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h00000000_00000097;
|
crc <= 64'h00000000_00000097;
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc==90) begin
|
else if (cyc==90) begin
|
||||||
if (sum !== 64'hf0afc2bfa78277c5) $stop;
|
if (sum !== 64'hf0afc2bfa78277c5) $stop;
|
||||||
end
|
end
|
||||||
else if (cyc==91) begin
|
else if (cyc==91) begin
|
||||||
end
|
end
|
||||||
|
|
@ -41,8 +41,8 @@ module t (/*AUTOARG*/
|
||||||
else if (cyc==94) begin
|
else if (cyc==94) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -56,7 +56,7 @@ module sub (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
|
|
||||||
input [23:0] in;
|
input [23:0] in;
|
||||||
output reg out1;
|
output reg out1;
|
||||||
output reg [4:0] out2;
|
output reg [4:0] out2;
|
||||||
|
|
||||||
always @* begin
|
always @* begin
|
||||||
|
|
@ -64,32 +64,32 @@ module sub (/*AUTOARG*/
|
||||||
casez (in[0])
|
casez (in[0])
|
||||||
endcase
|
endcase
|
||||||
casez (in)
|
casez (in)
|
||||||
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
|
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
|
||||||
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
|
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
|
||||||
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
|
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
|
||||||
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
|
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
|
||||||
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
|
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
|
||||||
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
|
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
|
||||||
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
|
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
|
||||||
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
|
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
|
||||||
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
|
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
|
||||||
// Same pattern, but reversed to test we work OK.
|
// Same pattern, but reversed to test we work OK.
|
||||||
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
|
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
|
||||||
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
|
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
|
||||||
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
|
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
|
||||||
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
|
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
|
||||||
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
|
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
|
||||||
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
|
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
|
||||||
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
|
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
|
||||||
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
|
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
|
||||||
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
|
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
|
||||||
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
|
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
|
||||||
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
|
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
|
||||||
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
|
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
|
||||||
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
|
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
|
||||||
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
|
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
|
||||||
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
|
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
|
||||||
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
|
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -19,45 +19,45 @@ module t (/*AUTOARG*/);
|
||||||
value = 4'b1001;
|
value = 4'b1001;
|
||||||
valuex = 4'b1xxx;
|
valuex = 4'b1xxx;
|
||||||
case (value)
|
case (value)
|
||||||
4'b1xxx: $stop;
|
4'b1xxx: $stop;
|
||||||
4'b1???: $stop;
|
4'b1???: $stop;
|
||||||
4'b1001: ;
|
4'b1001: ;
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
case (valuex)
|
case (valuex)
|
||||||
4'b1???: $stop;
|
4'b1???: $stop;
|
||||||
4'b1xxx: ;
|
4'b1xxx: ;
|
||||||
4'b1001: ;
|
4'b1001: ;
|
||||||
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
|
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
//
|
//
|
||||||
casex (value)
|
casex (value)
|
||||||
4'b100x: ;
|
4'b100x: ;
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
casex (value)
|
casex (value)
|
||||||
4'b100?: ;
|
4'b100?: ;
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
casex (valuex)
|
casex (valuex)
|
||||||
4'b100x: ;
|
4'b100x: ;
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
casex (valuex)
|
casex (valuex)
|
||||||
4'b100?: ;
|
4'b100?: ;
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
//
|
//
|
||||||
casez (value)
|
casez (value)
|
||||||
4'bxxxx: $stop;
|
4'bxxxx: $stop;
|
||||||
4'b100?: ;
|
4'b100?: ;
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
casez (valuex)
|
casez (valuex)
|
||||||
4'b1xx?: ;
|
4'b1xx?: ;
|
||||||
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
|
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
|
|
|
||||||
|
|
@ -59,8 +59,8 @@ module t;
|
||||||
logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11));
|
logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11));
|
||||||
// verilator lint_on WIDTH
|
// verilator lint_on WIDTH
|
||||||
logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector
|
logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector
|
||||||
(27'(coeff1 * samp1) >>> 11) +
|
(27'(coeff1 * samp1) >>> 11) +
|
||||||
(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
|
(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
|
||||||
|
|
||||||
logic one = 1'b1;
|
logic one = 1'b1;
|
||||||
logic [32:0] b33 = {32'(0), one};
|
logic [32:0] b33 = {32'(0), one};
|
||||||
|
|
|
||||||
|
|
@ -10,7 +10,7 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
input fastclk; // surefire lint_off_line UDDIXN
|
input fastclk; // surefire lint_off_line UDDIXN
|
||||||
|
|
||||||
integer _mode; initial _mode=0;
|
integer _mode; initial _mode=0;
|
||||||
|
|
||||||
|
|
@ -24,11 +24,11 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
// verilator lint_off UNOPT
|
// verilator lint_off UNOPT
|
||||||
t_chg_a a (
|
t_chg_a a (
|
||||||
.a(ord1), .a_p1(ord2),
|
.a(ord1), .a_p1(ord2),
|
||||||
.b(ord4), .b_p1(ord5),
|
.b(ord4), .b_p1(ord5),
|
||||||
.c(ord3), .c_p1(ord4),
|
.c(ord3), .c_p1(ord4),
|
||||||
.d(ord6), .d_p1(ord7)
|
.d(ord6), .d_p1(ord7)
|
||||||
);
|
);
|
||||||
|
|
||||||
// surefire lint_off ASWEMB
|
// surefire lint_off ASWEMB
|
||||||
assign ord6 = ord5 + 1;
|
assign ord6 = ord5 + 1;
|
||||||
|
|
@ -38,22 +38,22 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
|
always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
|
||||||
if (_mode==1) begin
|
if (_mode==1) begin
|
||||||
//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
|
//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
|
||||||
//if (ord2 == 2 && ord7 != 7) $stop;
|
//if (ord2 == 2 && ord7 != 7) $stop;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (_mode==0) begin
|
if (_mode==0) begin
|
||||||
$write("[%0t] t_chg: Running\n", $time);
|
$write("[%0t] t_chg: Running\n", $time);
|
||||||
_mode<=1;
|
_mode<=1;
|
||||||
ord1 <= 1;
|
ord1 <= 1;
|
||||||
end
|
end
|
||||||
else if (_mode==1) begin
|
else if (_mode==1) begin
|
||||||
_mode<=2;
|
_mode<=2;
|
||||||
if (ord7 !== 7) $stop;
|
if (ord7 !== 7) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -8,17 +8,17 @@
|
||||||
module t;
|
module t;
|
||||||
/*AUTOREGINPUT*/
|
/*AUTOREGINPUT*/
|
||||||
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
|
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
|
||||||
reg c0; // To t2 of t2.v
|
reg c0; // To t2 of t2.v
|
||||||
reg c1; // To t2 of t2.v
|
reg c1; // To t2 of t2.v
|
||||||
reg check; // To t2 of t2.v
|
reg check; // To t2 of t2.v
|
||||||
reg [1:0] clks; // To t2 of t2.v
|
reg [1:0] clks; // To t2 of t2.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
t2 t2 (/*AUTOINST*/
|
t2 t2 (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clks (clks[1:0]),
|
.clks (clks[1:0]),
|
||||||
.c0 (c0),
|
.c0 (c0),
|
||||||
.c1 (c1),
|
.c1 (c1),
|
||||||
.check (check));
|
.check (check));
|
||||||
task clockit (input v1, v0);
|
task clockit (input v1, v0);
|
||||||
c1 = v1;
|
c1 = v1;
|
||||||
c0 = v0;
|
c0 = v0;
|
||||||
|
|
@ -36,17 +36,17 @@ module t;
|
||||||
t2.clear();
|
t2.clear();
|
||||||
#10;
|
#10;
|
||||||
for (int i=0; i<2; i++) begin
|
for (int i=0; i<2; i++) begin
|
||||||
clockit(0, 0);
|
clockit(0, 0);
|
||||||
clockit(0, 0);
|
clockit(0, 0);
|
||||||
clockit(0, 1);
|
clockit(0, 1);
|
||||||
clockit(1, 1);
|
clockit(1, 1);
|
||||||
clockit(0, 0);
|
clockit(0, 0);
|
||||||
clockit(1, 1);
|
clockit(1, 1);
|
||||||
clockit(1, 0);
|
clockit(1, 0);
|
||||||
clockit(0, 0);
|
clockit(0, 0);
|
||||||
clockit(1, 0);
|
clockit(1, 0);
|
||||||
clockit(0, 1);
|
clockit(0, 1);
|
||||||
clockit(0, 0);
|
clockit(0, 0);
|
||||||
end
|
end
|
||||||
check = 1;
|
check = 1;
|
||||||
clockit(0, 0);
|
clockit(0, 0);
|
||||||
|
|
@ -61,10 +61,10 @@ endmodule
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
module `t2 (
|
module `t2 (
|
||||||
input [1:0] clks,
|
input [1:0] clks,
|
||||||
input c0,
|
input c0,
|
||||||
input c1,
|
input c1,
|
||||||
input check
|
input check
|
||||||
);
|
);
|
||||||
|
|
||||||
`ifdef T_CLK_2IN_VEC
|
`ifdef T_CLK_2IN_VEC
|
||||||
|
|
|
||||||
|
|
@ -5,11 +5,11 @@
|
||||||
// SPDX-License-Identifier: CC0-1.0
|
// SPDX-License-Identifier: CC0-1.0
|
||||||
|
|
||||||
module some_module (
|
module some_module (
|
||||||
input wrclk
|
input wrclk
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [ 1 : 0 ] some_state;
|
logic [ 1 : 0 ] some_state;
|
||||||
logic [1:0] some_other_state;
|
logic [1:0] some_other_state;
|
||||||
|
|
||||||
always @(posedge wrclk) begin
|
always @(posedge wrclk) begin
|
||||||
case (some_state)
|
case (some_state)
|
||||||
|
|
@ -29,31 +29,31 @@ endmodule
|
||||||
`define BROKEN
|
`define BROKEN
|
||||||
|
|
||||||
module t1(
|
module t1(
|
||||||
input [3:0] i_clks,
|
input [3:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1
|
input i_clk1
|
||||||
);
|
);
|
||||||
|
|
||||||
some_module
|
some_module
|
||||||
some_module
|
some_module
|
||||||
(
|
(
|
||||||
`ifdef BROKEN
|
`ifdef BROKEN
|
||||||
.wrclk (i_clks[3])
|
.wrclk (i_clks[3])
|
||||||
`else
|
`else
|
||||||
.wrclk (i_clk1)
|
.wrclk (i_clk1)
|
||||||
`endif
|
`endif
|
||||||
);
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t2(
|
module t2(
|
||||||
input [2:0] i_clks,
|
input [2:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1,
|
input i_clk1,
|
||||||
input i_clk2,
|
input i_clk2,
|
||||||
input i_data
|
input i_data
|
||||||
);
|
);
|
||||||
logic [3:0] the_clks;
|
logic [3:0] the_clks;
|
||||||
logic data_q;
|
logic data_q;
|
||||||
|
|
||||||
assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0};
|
assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0};
|
||||||
|
|
||||||
|
|
@ -71,16 +71,16 @@ endmodule
|
||||||
|
|
||||||
module t(
|
module t(
|
||||||
`ifdef ATTRIBUTES
|
`ifdef ATTRIBUTES
|
||||||
input clk0 /*verilator clocker*/,
|
input clk0 /*verilator clocker*/,
|
||||||
input clk1 /*verilator clocker*/,
|
input clk1 /*verilator clocker*/,
|
||||||
input clk2 /*verilator clocker*/,
|
input clk2 /*verilator clocker*/,
|
||||||
`else
|
`else
|
||||||
input clk0,
|
input clk0,
|
||||||
input clk1,
|
input clk1,
|
||||||
input clk2,
|
input clk2,
|
||||||
`endif
|
`endif
|
||||||
input data_in
|
input data_in
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [2:0] clks;
|
logic [2:0] clks;
|
||||||
|
|
||||||
|
|
@ -89,12 +89,12 @@ module t(
|
||||||
t2
|
t2
|
||||||
t2
|
t2
|
||||||
(
|
(
|
||||||
.i_clks (clks),
|
.i_clks (clks),
|
||||||
.i_clk0 (clk0),
|
.i_clk0 (clk0),
|
||||||
.i_clk1 (clk1),
|
.i_clk1 (clk1),
|
||||||
.i_clk2 (clk2),
|
.i_clk2 (clk2),
|
||||||
.i_data (data_in)
|
.i_data (data_in)
|
||||||
);
|
);
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
|
|
|
||||||
|
|
@ -5,11 +5,11 @@
|
||||||
// SPDX-License-Identifier: CC0-1.0
|
// SPDX-License-Identifier: CC0-1.0
|
||||||
|
|
||||||
module some_module (
|
module some_module (
|
||||||
input wrclk
|
input wrclk
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [ 1 : 0 ] some_state;
|
logic [ 1 : 0 ] some_state;
|
||||||
logic [1:0] some_other_state;
|
logic [1:0] some_other_state;
|
||||||
|
|
||||||
always @(posedge wrclk) begin
|
always @(posedge wrclk) begin
|
||||||
case (some_state)
|
case (some_state)
|
||||||
|
|
@ -29,31 +29,31 @@ endmodule
|
||||||
`define BROKEN
|
`define BROKEN
|
||||||
|
|
||||||
module t1(
|
module t1(
|
||||||
input [3:0] i_clks,
|
input [3:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1
|
input i_clk1
|
||||||
);
|
);
|
||||||
|
|
||||||
some_module
|
some_module
|
||||||
some_module
|
some_module
|
||||||
(
|
(
|
||||||
`ifdef BROKEN
|
`ifdef BROKEN
|
||||||
.wrclk (i_clks[3])
|
.wrclk (i_clks[3])
|
||||||
`else
|
`else
|
||||||
.wrclk (i_clk1)
|
.wrclk (i_clk1)
|
||||||
`endif
|
`endif
|
||||||
);
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t2(
|
module t2(
|
||||||
input [2:0] i_clks,
|
input [2:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1,
|
input i_clk1,
|
||||||
input i_clk2,
|
input i_clk2,
|
||||||
input i_data
|
input i_data
|
||||||
);
|
);
|
||||||
logic [3:0] the_clks;
|
logic [3:0] the_clks;
|
||||||
logic data_q;
|
logic data_q;
|
||||||
|
|
||||||
assign the_clks[3] = i_clk1;
|
assign the_clks[3] = i_clk1;
|
||||||
assign the_clks[2] = i_clk2;
|
assign the_clks[2] = i_clk2;
|
||||||
|
|
@ -73,14 +73,14 @@ module t2(
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t(
|
module t(
|
||||||
/*AUTOARG*/
|
/*AUTOARG*/
|
||||||
// Inputs
|
// Inputs
|
||||||
clk /*verilator clocker*/,
|
clk /*verilator clocker*/,
|
||||||
input clk0 /*verilator clocker*/,
|
input clk0 /*verilator clocker*/,
|
||||||
input clk1 /*verilator clocker*/,
|
input clk1 /*verilator clocker*/,
|
||||||
input clk2 /*verilator clocker*/,
|
input clk2 /*verilator clocker*/,
|
||||||
input data_in
|
input data_in
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
|
|
@ -91,12 +91,12 @@ module t(
|
||||||
t2
|
t2
|
||||||
t2
|
t2
|
||||||
(
|
(
|
||||||
.i_clks (clks),
|
.i_clks (clks),
|
||||||
.i_clk0 (clk0),
|
.i_clk0 (clk0),
|
||||||
.i_clk1 (clk),
|
.i_clk1 (clk),
|
||||||
.i_clk2 (clk2),
|
.i_clk2 (clk2),
|
||||||
.i_data (data_in)
|
.i_data (data_in)
|
||||||
);
|
);
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
|
|
|
||||||
|
|
@ -6,11 +6,11 @@
|
||||||
|
|
||||||
/* verilator lint_off LITENDIAN */
|
/* verilator lint_off LITENDIAN */
|
||||||
module some_module (
|
module some_module (
|
||||||
input wrclk
|
input wrclk
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [ 1 : 0 ] some_state;
|
logic [ 1 : 0 ] some_state;
|
||||||
logic [1:0] some_other_state;
|
logic [1:0] some_other_state;
|
||||||
|
|
||||||
always @(posedge wrclk) begin
|
always @(posedge wrclk) begin
|
||||||
case (some_state)
|
case (some_state)
|
||||||
|
|
@ -30,31 +30,31 @@ endmodule
|
||||||
`define BROKEN
|
`define BROKEN
|
||||||
|
|
||||||
module t1(
|
module t1(
|
||||||
input [-12:-9] i_clks,
|
input [-12:-9] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1
|
input i_clk1
|
||||||
);
|
);
|
||||||
|
|
||||||
some_module
|
some_module
|
||||||
some_module
|
some_module
|
||||||
(
|
(
|
||||||
`ifdef BROKEN
|
`ifdef BROKEN
|
||||||
.wrclk (i_clks[-12])
|
.wrclk (i_clks[-12])
|
||||||
`else
|
`else
|
||||||
.wrclk (i_clk1)
|
.wrclk (i_clk1)
|
||||||
`endif
|
`endif
|
||||||
);
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t2(
|
module t2(
|
||||||
input [2:0] i_clks,
|
input [2:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1,
|
input i_clk1,
|
||||||
input i_clk2,
|
input i_clk2,
|
||||||
input i_data
|
input i_data
|
||||||
);
|
);
|
||||||
logic [-12:-9] the_clks;
|
logic [-12:-9] the_clks;
|
||||||
logic data_q;
|
logic data_q;
|
||||||
|
|
||||||
assign the_clks[-12] = i_clk1;
|
assign the_clks[-12] = i_clk1;
|
||||||
assign the_clks[-11] = i_clk2;
|
assign the_clks[-11] = i_clk2;
|
||||||
|
|
@ -74,11 +74,11 @@ module t2(
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t(
|
module t(
|
||||||
input clk0 /*verilator clocker*/,
|
input clk0 /*verilator clocker*/,
|
||||||
input clk1 /*verilator clocker*/,
|
input clk1 /*verilator clocker*/,
|
||||||
input clk2 /*verilator clocker*/,
|
input clk2 /*verilator clocker*/,
|
||||||
input data_in
|
input data_in
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [2:0] clks;
|
logic [2:0] clks;
|
||||||
|
|
||||||
|
|
@ -87,12 +87,12 @@ module t(
|
||||||
t2
|
t2
|
||||||
t2
|
t2
|
||||||
(
|
(
|
||||||
.i_clks (clks),
|
.i_clks (clks),
|
||||||
.i_clk0 (clk0),
|
.i_clk0 (clk0),
|
||||||
.i_clk1 (clk1),
|
.i_clk1 (clk1),
|
||||||
.i_clk2 (clk2),
|
.i_clk2 (clk2),
|
||||||
.i_data (data_in)
|
.i_data (data_in)
|
||||||
);
|
);
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
|
|
|
||||||
|
|
@ -5,11 +5,11 @@
|
||||||
// SPDX-License-Identifier: CC0-1.0
|
// SPDX-License-Identifier: CC0-1.0
|
||||||
|
|
||||||
module some_module (
|
module some_module (
|
||||||
input wrclk
|
input wrclk
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [ 1 : 0 ] some_state;
|
logic [ 1 : 0 ] some_state;
|
||||||
logic [1:0] some_other_state;
|
logic [1:0] some_other_state;
|
||||||
|
|
||||||
always @(posedge wrclk) begin
|
always @(posedge wrclk) begin
|
||||||
case (some_state)
|
case (some_state)
|
||||||
|
|
@ -29,36 +29,36 @@ endmodule
|
||||||
`define BROKEN
|
`define BROKEN
|
||||||
|
|
||||||
module t1(
|
module t1(
|
||||||
input [3:0] i_clks,
|
input [3:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1
|
input i_clk1
|
||||||
);
|
);
|
||||||
|
|
||||||
generate
|
generate
|
||||||
genvar i;
|
genvar i;
|
||||||
for (i = 0; i < 2; i = i + 1) begin: a_generate_block
|
for (i = 0; i < 2; i = i + 1) begin: a_generate_block
|
||||||
some_module
|
some_module
|
||||||
some_module
|
some_module
|
||||||
(
|
(
|
||||||
`ifdef BROKEN
|
`ifdef BROKEN
|
||||||
.wrclk (i_clks[3])
|
.wrclk (i_clks[3])
|
||||||
`else
|
`else
|
||||||
.wrclk (i_clk1)
|
.wrclk (i_clk1)
|
||||||
`endif
|
`endif
|
||||||
);
|
);
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t2(
|
module t2(
|
||||||
input [2:0] i_clks,
|
input [2:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1,
|
input i_clk1,
|
||||||
input i_clk2,
|
input i_clk2,
|
||||||
input i_data
|
input i_data
|
||||||
);
|
);
|
||||||
logic [3:0] the_clks;
|
logic [3:0] the_clks;
|
||||||
logic data_q;
|
logic data_q;
|
||||||
|
|
||||||
assign the_clks[3] = i_clk1;
|
assign the_clks[3] = i_clk1;
|
||||||
assign the_clks[2] = i_clk2;
|
assign the_clks[2] = i_clk2;
|
||||||
|
|
@ -78,11 +78,11 @@ module t2(
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t(
|
module t(
|
||||||
input clk0 /*verilator clocker*/,
|
input clk0 /*verilator clocker*/,
|
||||||
input clk1 /*verilator clocker*/,
|
input clk1 /*verilator clocker*/,
|
||||||
input clk2 /*verilator clocker*/,
|
input clk2 /*verilator clocker*/,
|
||||||
input data_in
|
input data_in
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [2:0] clks;
|
logic [2:0] clks;
|
||||||
|
|
||||||
|
|
@ -91,12 +91,12 @@ module t(
|
||||||
t2
|
t2
|
||||||
t2
|
t2
|
||||||
(
|
(
|
||||||
.i_clks (clks),
|
.i_clks (clks),
|
||||||
.i_clk0 (clk0),
|
.i_clk0 (clk0),
|
||||||
.i_clk1 (clk1),
|
.i_clk1 (clk1),
|
||||||
.i_clk2 (clk2),
|
.i_clk2 (clk2),
|
||||||
.i_data (data_in)
|
.i_data (data_in)
|
||||||
);
|
);
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
|
|
|
||||||
|
|
@ -5,11 +5,11 @@
|
||||||
// SPDX-License-Identifier: CC0-1.0
|
// SPDX-License-Identifier: CC0-1.0
|
||||||
|
|
||||||
module some_module (
|
module some_module (
|
||||||
input [3:0] i_clks
|
input [3:0] i_clks
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [ 1 : 0 ] some_state;
|
logic [ 1 : 0 ] some_state;
|
||||||
logic [1:0] some_other_state;
|
logic [1:0] some_other_state;
|
||||||
|
|
||||||
always @(posedge i_clks[3]) begin
|
always @(posedge i_clks[3]) begin
|
||||||
case (some_state)
|
case (some_state)
|
||||||
|
|
@ -32,27 +32,27 @@ endmodule
|
||||||
`define BROKEN
|
`define BROKEN
|
||||||
|
|
||||||
module t1(
|
module t1(
|
||||||
input [3:0] i_clks,
|
input [3:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1
|
input i_clk1
|
||||||
);
|
);
|
||||||
|
|
||||||
some_module
|
some_module
|
||||||
some_module
|
some_module
|
||||||
(
|
(
|
||||||
.i_clks (i_clks)
|
.i_clks (i_clks)
|
||||||
);
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t2(
|
module t2(
|
||||||
input [2:0] i_clks,
|
input [2:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1,
|
input i_clk1,
|
||||||
input i_clk2,
|
input i_clk2,
|
||||||
input i_data
|
input i_data
|
||||||
);
|
);
|
||||||
logic [3:0] the_clks;
|
logic [3:0] the_clks;
|
||||||
logic data_q;
|
logic data_q;
|
||||||
|
|
||||||
assign the_clks[3] = i_clk1;
|
assign the_clks[3] = i_clk1;
|
||||||
assign the_clks[2] = i_clk2;
|
assign the_clks[2] = i_clk2;
|
||||||
|
|
@ -72,14 +72,14 @@ module t2(
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t(
|
module t(
|
||||||
/*AUTOARG*/
|
/*AUTOARG*/
|
||||||
// Inputs
|
// Inputs
|
||||||
clk /*verilator clocker*/,
|
clk /*verilator clocker*/,
|
||||||
input clk0 /*verilator clocker*/,
|
input clk0 /*verilator clocker*/,
|
||||||
input clk1 /*verilator clocker*/,
|
input clk1 /*verilator clocker*/,
|
||||||
input clk2 /*verilator clocker*/,
|
input clk2 /*verilator clocker*/,
|
||||||
input data_in
|
input data_in
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
|
|
@ -90,12 +90,12 @@ module t(
|
||||||
t2
|
t2
|
||||||
t2
|
t2
|
||||||
(
|
(
|
||||||
.i_clks (clks),
|
.i_clks (clks),
|
||||||
.i_clk0 (clk0),
|
.i_clk0 (clk0),
|
||||||
.i_clk1 (clk),
|
.i_clk1 (clk),
|
||||||
.i_clk2 (clk2),
|
.i_clk2 (clk2),
|
||||||
.i_data (data_in)
|
.i_data (data_in)
|
||||||
);
|
);
|
||||||
|
|
||||||
// initial begin
|
// initial begin
|
||||||
// $write("*-* All Finished *-*\n");
|
// $write("*-* All Finished *-*\n");
|
||||||
|
|
|
||||||
|
|
@ -5,12 +5,12 @@
|
||||||
// SPDX-License-Identifier: CC0-1.0
|
// SPDX-License-Identifier: CC0-1.0
|
||||||
|
|
||||||
module some_module (
|
module some_module (
|
||||||
input [3:0] i_clks
|
input [3:0] i_clks
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [ 1 : 0 ] some_state;
|
logic [ 1 : 0 ] some_state;
|
||||||
logic [1:0] some_other_state;
|
logic [1:0] some_other_state;
|
||||||
logic the_clk;
|
logic the_clk;
|
||||||
|
|
||||||
assign the_clk = i_clks[3];
|
assign the_clk = i_clks[3];
|
||||||
|
|
||||||
|
|
@ -35,35 +35,35 @@ endmodule
|
||||||
`define BROKEN
|
`define BROKEN
|
||||||
|
|
||||||
module t1(
|
module t1(
|
||||||
input [3:0] i_clks,
|
input [3:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1
|
input i_clk1
|
||||||
);
|
);
|
||||||
|
|
||||||
some_module
|
some_module
|
||||||
some_module
|
some_module
|
||||||
(
|
(
|
||||||
.i_clks (i_clks)
|
.i_clks (i_clks)
|
||||||
);
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module ident(
|
module ident(
|
||||||
input i_ident,
|
input i_ident,
|
||||||
output o_ident
|
output o_ident
|
||||||
);
|
);
|
||||||
assign o_ident = i_ident;
|
assign o_ident = i_ident;
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t2(
|
module t2(
|
||||||
input [2:0] i_clks,
|
input [2:0] i_clks,
|
||||||
input i_clk0,
|
input i_clk0,
|
||||||
input i_clk1,
|
input i_clk1,
|
||||||
input i_clk2,
|
input i_clk2,
|
||||||
input i_data
|
input i_data
|
||||||
);
|
);
|
||||||
logic [3:0] the_clks;
|
logic [3:0] the_clks;
|
||||||
logic data_q;
|
logic data_q;
|
||||||
logic ident_clk1;
|
logic ident_clk1;
|
||||||
|
|
||||||
always @(posedge i_clk0) begin
|
always @(posedge i_clk0) begin
|
||||||
data_q <= i_data;
|
data_q <= i_data;
|
||||||
|
|
@ -72,9 +72,9 @@ module t2(
|
||||||
ident
|
ident
|
||||||
ident
|
ident
|
||||||
(
|
(
|
||||||
.i_ident (i_clk1),
|
.i_ident (i_clk1),
|
||||||
.o_ident (ident_clk1)
|
.o_ident (ident_clk1)
|
||||||
);
|
);
|
||||||
|
|
||||||
t1 t1
|
t1 t1
|
||||||
(
|
(
|
||||||
|
|
@ -85,14 +85,14 @@ module t2(
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t(
|
module t(
|
||||||
/*AUTOARG*/
|
/*AUTOARG*/
|
||||||
// Inputs
|
// Inputs
|
||||||
clk /*verilator clocker*/ /*verilator public_flat*/,
|
clk /*verilator clocker*/ /*verilator public_flat*/,
|
||||||
input clk0 /*verilator clocker*/,
|
input clk0 /*verilator clocker*/,
|
||||||
input clk1 /*verilator clocker*/,
|
input clk1 /*verilator clocker*/,
|
||||||
input clk2 /*verilator clocker*/,
|
input clk2 /*verilator clocker*/,
|
||||||
input data_in
|
input data_in
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
|
|
@ -103,11 +103,11 @@ module t(
|
||||||
t2
|
t2
|
||||||
t2
|
t2
|
||||||
(
|
(
|
||||||
.i_clks (clks),
|
.i_clks (clks),
|
||||||
.i_clk0 (clk0),
|
.i_clk0 (clk0),
|
||||||
.i_clk1 (clk),
|
.i_clk1 (clk),
|
||||||
.i_clk2 (clk2),
|
.i_clk2 (clk2),
|
||||||
.i_data (data_in)
|
.i_data (data_in)
|
||||||
);
|
);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -16,7 +16,7 @@ module t (clk);
|
||||||
wire [7:0] q8;
|
wire [7:0] q8;
|
||||||
|
|
||||||
// verilator lint_off UNOPTFLAT
|
// verilator lint_off UNOPTFLAT
|
||||||
reg ena;
|
reg ena;
|
||||||
// verilator lint_on UNOPTFLAT
|
// verilator lint_on UNOPTFLAT
|
||||||
|
|
||||||
condff #(12) condff
|
condff #(12) condff
|
||||||
|
|
@ -27,42 +27,42 @@ module t (clk);
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
|
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
|
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
|
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
|
||||||
ena <= 1'b0;
|
ena <= 1'b0;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
|
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
if (q8 != 8'h11) $stop;
|
if (q8 != 8'h11) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
|
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
if (q8 != 8'h11) $stop;
|
if (q8 != 8'h11) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==5) begin
|
if (cyc==5) begin
|
||||||
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
|
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
if (q8 != 8'h44) $stop;
|
if (q8 != 8'h44) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==6) begin
|
if (cyc==6) begin
|
||||||
if (q8 != 8'h77) $stop;
|
if (q8 != 8'h77) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==7) begin
|
if (cyc==7) begin
|
||||||
if (q8 != 8'h88) $stop;
|
if (q8 != 8'h88) $stop;
|
||||||
end
|
end
|
||||||
//
|
//
|
||||||
if (cyc==20) begin
|
if (cyc==20) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
@ -93,22 +93,22 @@ module condffimp (clk, sen, ena, d, q);
|
||||||
|
|
||||||
always @(posedge gatedclk) begin
|
always @(posedge gatedclk) begin
|
||||||
if (gatedclk === 1'bX) begin
|
if (gatedclk === 1'bX) begin
|
||||||
q <= {WIDTH{1'bX}};
|
q <= {WIDTH{1'bX}};
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
q <= d;
|
q <= d;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module clockgate (clk, sen, ena, gatedclk);
|
module clockgate (clk, sen, ena, gatedclk);
|
||||||
input clk;
|
input clk;
|
||||||
input sen;
|
input sen;
|
||||||
input ena;
|
input ena;
|
||||||
output gatedclk;
|
output gatedclk;
|
||||||
|
|
||||||
reg ena_b;
|
reg ena_b;
|
||||||
wire gatedclk = clk & ena_b;
|
wire gatedclk = clk & ena_b;
|
||||||
|
|
||||||
// verilator lint_off COMBDLY
|
// verilator lint_off COMBDLY
|
||||||
|
|
@ -118,7 +118,7 @@ module clockgate (clk, sen, ena, gatedclk);
|
||||||
ena_b <= ena | sen;
|
ena_b <= ena | sen;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if ((clk^sen)===1'bX) ena_b <= 1'bX;
|
if ((clk^sen)===1'bX) ena_b <= 1'bX;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
// verilator lint_on LATCH
|
// verilator lint_on LATCH
|
||||||
|
|
|
||||||
|
|
@ -16,7 +16,7 @@ module t (clk);
|
||||||
wire [7:0] q8;
|
wire [7:0] q8;
|
||||||
|
|
||||||
// verilator lint_off UNOPTFLAT
|
// verilator lint_off UNOPTFLAT
|
||||||
reg ena;
|
reg ena;
|
||||||
// verilator lint_on UNOPTFLAT
|
// verilator lint_on UNOPTFLAT
|
||||||
|
|
||||||
condff #(12) condff
|
condff #(12) condff
|
||||||
|
|
@ -27,42 +27,42 @@ module t (clk);
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
|
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
|
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
|
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
|
||||||
ena <= 1'b0;
|
ena <= 1'b0;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
|
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
if (q8 != 8'h11) $stop;
|
if (q8 != 8'h11) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
|
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
if (q8 != 8'h11) $stop;
|
if (q8 != 8'h11) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==5) begin
|
if (cyc==5) begin
|
||||||
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
|
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
|
||||||
ena <= 1'b1;
|
ena <= 1'b1;
|
||||||
if (q8 != 8'h44) $stop;
|
if (q8 != 8'h44) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==6) begin
|
if (cyc==6) begin
|
||||||
if (q8 != 8'h77) $stop;
|
if (q8 != 8'h77) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==7) begin
|
if (cyc==7) begin
|
||||||
if (q8 != 8'h88) $stop;
|
if (q8 != 8'h88) $stop;
|
||||||
end
|
end
|
||||||
//
|
//
|
||||||
if (cyc==20) begin
|
if (cyc==20) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
@ -93,22 +93,22 @@ module condffimp (clk, sen, ena, d, q);
|
||||||
|
|
||||||
always @(posedge gatedclk) begin
|
always @(posedge gatedclk) begin
|
||||||
if (gatedclk === 1'bX) begin
|
if (gatedclk === 1'bX) begin
|
||||||
q <= {WIDTH{1'bX}};
|
q <= {WIDTH{1'bX}};
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
q <= d;
|
q <= d;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module clockgate (clk, sen, ena, gatedclk);
|
module clockgate (clk, sen, ena, gatedclk);
|
||||||
input clk;
|
input clk;
|
||||||
input sen;
|
input sen;
|
||||||
input ena;
|
input ena;
|
||||||
output gatedclk;
|
output gatedclk;
|
||||||
|
|
||||||
reg ena_b;
|
reg ena_b;
|
||||||
wire gatedclk = clk & ena_b;
|
wire gatedclk = clk & ena_b;
|
||||||
|
|
||||||
// verilator lint_off COMBDLY
|
// verilator lint_off COMBDLY
|
||||||
|
|
@ -118,7 +118,7 @@ module clockgate (clk, sen, ena, gatedclk);
|
||||||
ena_b <= ena | sen;
|
ena_b <= ena | sen;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if ((clk^sen)===1'bX) ena_b <= 1'bX;
|
if ((clk^sen)===1'bX) ena_b <= 1'bX;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
// verilator lint_on LATCH
|
// verilator lint_on LATCH
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ module t (/*AUTOARG*/
|
||||||
// verilator lint_off GENCLK
|
// verilator lint_off GENCLK
|
||||||
|
|
||||||
reg [7:0] cyc; initial cyc = 0;
|
reg [7:0] cyc; initial cyc = 0;
|
||||||
reg genclk;
|
reg genclk;
|
||||||
// verilator lint_off MULTIDRIVEN
|
// verilator lint_off MULTIDRIVEN
|
||||||
reg [7:0] set_both;
|
reg [7:0] set_both;
|
||||||
// verilator lint_on MULTIDRIVEN
|
// verilator lint_on MULTIDRIVEN
|
||||||
|
|
@ -27,14 +27,14 @@ module t (/*AUTOARG*/
|
||||||
set_both <= cyc;
|
set_both <= cyc;
|
||||||
$write ("SB set_both %x <= cyc %x\n", set_both, cyc);
|
$write ("SB set_both %x <= cyc %x\n", set_both, cyc);
|
||||||
if (genthiscyc) begin
|
if (genthiscyc) begin
|
||||||
if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
|
if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop;
|
if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==10) begin
|
if (cyc==10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -15,62 +15,62 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
reg [7:0] cyc; initial cyc = 0;
|
reg [7:0] cyc; initial cyc = 0;
|
||||||
reg [7:0] padd;
|
reg [7:0] padd;
|
||||||
reg dsp_ph1, dsp_ph2, dsp_reset;
|
reg dsp_ph1, dsp_ph2, dsp_reset;
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [7:0] out; // From dspchip of t_dspchip.v
|
wire [7:0] out; // From dspchip of t_dspchip.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
t_dspchip dspchip (/*AUTOINST*/
|
t_dspchip dspchip (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out (out[7:0]),
|
.out (out[7:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.dsp_ph1 (dsp_ph1),
|
.dsp_ph1 (dsp_ph1),
|
||||||
.dsp_ph2 (dsp_ph2),
|
.dsp_ph2 (dsp_ph2),
|
||||||
.dsp_reset (dsp_reset),
|
.dsp_reset (dsp_reset),
|
||||||
.padd (padd[7:0]));
|
.padd (padd[7:0]));
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
$write("cyc %d\n",cyc);
|
$write("cyc %d\n",cyc);
|
||||||
if (cyc == 8'd0) begin
|
if (cyc == 8'd0) begin
|
||||||
cyc <= 8'd1;
|
cyc <= 8'd1;
|
||||||
dsp_reset <= 0; // Need a posedge
|
dsp_reset <= 0; // Need a posedge
|
||||||
padd <= 0;
|
padd <= 0;
|
||||||
end
|
end
|
||||||
else if (cyc == 8'd20) begin
|
else if (cyc == 8'd20) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
cyc <= cyc + 8'd1;
|
cyc <= cyc + 8'd1;
|
||||||
dsp_ph1 <= ((cyc&8'd3) == 8'd0);
|
dsp_ph1 <= ((cyc&8'd3) == 8'd0);
|
||||||
dsp_ph2 <= ((cyc&8'd3) == 8'd2);
|
dsp_ph2 <= ((cyc&8'd3) == 8'd2);
|
||||||
dsp_reset <= (cyc == 8'd1);
|
dsp_reset <= (cyc == 8'd1);
|
||||||
padd <= cyc;
|
padd <= cyc;
|
||||||
//$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out);
|
//$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out);
|
||||||
case (cyc)
|
case (cyc)
|
||||||
default: $stop;
|
default: $stop;
|
||||||
8'd01: ;
|
8'd01: ;
|
||||||
8'd02: ;
|
8'd02: ;
|
||||||
8'd03: ;
|
8'd03: ;
|
||||||
8'd04: ;
|
8'd04: ;
|
||||||
8'd05: ;
|
8'd05: ;
|
||||||
8'd06: ;
|
8'd06: ;
|
||||||
8'd07: ;
|
8'd07: ;
|
||||||
8'd08: ;
|
8'd08: ;
|
||||||
8'd09: if (out!==8'h04) $stop;
|
8'd09: if (out!==8'h04) $stop;
|
||||||
8'd10: if (out!==8'h04) $stop;
|
8'd10: if (out!==8'h04) $stop;
|
||||||
8'd11: if (out!==8'h08) $stop;
|
8'd11: if (out!==8'h08) $stop;
|
||||||
8'd12: if (out!==8'h08) $stop;
|
8'd12: if (out!==8'h08) $stop;
|
||||||
8'd13: if (out!==8'h00) $stop;
|
8'd13: if (out!==8'h00) $stop;
|
||||||
8'd14: if (out!==8'h00) $stop;
|
8'd14: if (out!==8'h00) $stop;
|
||||||
8'd15: if (out!==8'h00) $stop;
|
8'd15: if (out!==8'h00) $stop;
|
||||||
8'd16: if (out!==8'h00) $stop;
|
8'd16: if (out!==8'h00) $stop;
|
||||||
8'd17: if (out!==8'h0c) $stop;
|
8'd17: if (out!==8'h0c) $stop;
|
||||||
8'd18: if (out!==8'h0c) $stop;
|
8'd18: if (out!==8'h0c) $stop;
|
||||||
8'd19: if (out!==8'h10) $stop;
|
8'd19: if (out!==8'h10) $stop;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -86,34 +86,34 @@ module t_dspchip (/*AUTOARG*/
|
||||||
input [7:0] padd;
|
input [7:0] padd;
|
||||||
output [7:0] out;
|
output [7:0] out;
|
||||||
|
|
||||||
wire dsp_ph1, dsp_ph2;
|
wire dsp_ph1, dsp_ph2;
|
||||||
wire [7:0] out;
|
wire [7:0] out;
|
||||||
wire pla_ph1, pla_ph2;
|
wire pla_ph1, pla_ph2;
|
||||||
wire out1_r;
|
wire out1_r;
|
||||||
wire [7:0] out2_r, padd;
|
wire [7:0] out2_r, padd;
|
||||||
wire clk_en;
|
wire clk_en;
|
||||||
|
|
||||||
t_dspcore t_dspcore (/*AUTOINST*/
|
t_dspcore t_dspcore (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out1_r (out1_r),
|
.out1_r (out1_r),
|
||||||
.pla_ph1 (pla_ph1),
|
.pla_ph1 (pla_ph1),
|
||||||
.pla_ph2 (pla_ph2),
|
.pla_ph2 (pla_ph2),
|
||||||
// Inputs
|
// Inputs
|
||||||
.dsp_ph1 (dsp_ph1),
|
.dsp_ph1 (dsp_ph1),
|
||||||
.dsp_ph2 (dsp_ph2),
|
.dsp_ph2 (dsp_ph2),
|
||||||
.dsp_reset (dsp_reset),
|
.dsp_reset (dsp_reset),
|
||||||
.clk_en (clk_en));
|
.clk_en (clk_en));
|
||||||
t_dsppla t_dsppla (/*AUTOINST*/
|
t_dsppla t_dsppla (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out2_r (out2_r[7:0]),
|
.out2_r (out2_r[7:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.pla_ph1 (pla_ph1),
|
.pla_ph1 (pla_ph1),
|
||||||
.pla_ph2 (pla_ph2),
|
.pla_ph2 (pla_ph2),
|
||||||
.dsp_reset (dsp_reset),
|
.dsp_reset (dsp_reset),
|
||||||
.padd (padd[7:0]));
|
.padd (padd[7:0]));
|
||||||
|
|
||||||
assign out = out1_r ? 8'h00 : out2_r;
|
assign out = out1_r ? 8'h00 : out2_r;
|
||||||
assign clk_en = 1'b1;
|
assign clk_en = 1'b1;
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
@ -129,13 +129,13 @@ module t_dspcore (/*AUTOARG*/
|
||||||
|
|
||||||
wire dsp_ph1, dsp_ph2, dsp_reset;
|
wire dsp_ph1, dsp_ph2, dsp_reset;
|
||||||
wire pla_ph1, pla_ph2;
|
wire pla_ph1, pla_ph2;
|
||||||
reg out1_r;
|
reg out1_r;
|
||||||
|
|
||||||
always @(posedge dsp_ph1 or posedge dsp_reset) begin
|
always @(posedge dsp_ph1 or posedge dsp_reset) begin
|
||||||
if (dsp_reset)
|
if (dsp_reset)
|
||||||
out1_r <= 1'h0;
|
out1_r <= 1'h0;
|
||||||
else
|
else
|
||||||
out1_r <= ~out1_r;
|
out1_r <= ~out1_r;
|
||||||
end
|
end
|
||||||
|
|
||||||
assign pla_ph1 = dsp_ph1;
|
assign pla_ph1 = dsp_ph1;
|
||||||
|
|
@ -153,24 +153,24 @@ module t_dsppla (/*AUTOARG*/
|
||||||
input [7:0] padd;
|
input [7:0] padd;
|
||||||
output [7:0] out2_r;
|
output [7:0] out2_r;
|
||||||
|
|
||||||
wire pla_ph1, pla_ph2, dsp_reset;
|
wire pla_ph1, pla_ph2, dsp_reset;
|
||||||
wire [7:0] padd;
|
wire [7:0] padd;
|
||||||
reg [7:0] out2_r;
|
reg [7:0] out2_r;
|
||||||
|
|
||||||
reg [7:0] latched_r;
|
reg [7:0] latched_r;
|
||||||
|
|
||||||
always @(posedge pla_ph1 or posedge dsp_reset) begin
|
always @(posedge pla_ph1 or posedge dsp_reset) begin
|
||||||
if (dsp_reset)
|
if (dsp_reset)
|
||||||
latched_r <= 8'h00;
|
latched_r <= 8'h00;
|
||||||
else
|
else
|
||||||
latched_r <= padd;
|
latched_r <= padd;
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(posedge pla_ph2 or posedge dsp_reset) begin
|
always @(posedge pla_ph2 or posedge dsp_reset) begin
|
||||||
if (dsp_reset)
|
if (dsp_reset)
|
||||||
out2_r <= 8'h00;
|
out2_r <= 8'h00;
|
||||||
else
|
else
|
||||||
out2_r <= latched_r;
|
out2_r <= latched_r;
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -11,7 +11,7 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
input fastclk;
|
input fastclk;
|
||||||
reg reset_l;
|
reg reset_l;
|
||||||
|
|
||||||
int cyc;
|
int cyc;
|
||||||
initial reset_l = 0;
|
initial reset_l = 0;
|
||||||
|
|
@ -22,10 +22,10 @@ module t (/*AUTOARG*/
|
||||||
end
|
end
|
||||||
|
|
||||||
t_clk t (/*AUTOINST*/
|
t_clk t (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.fastclk (fastclk),
|
.fastclk (fastclk),
|
||||||
.reset_l (reset_l));
|
.reset_l (reset_l));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module t_clk (/*AUTOARG*/
|
module t_clk (/*AUTOARG*/
|
||||||
|
|
@ -40,7 +40,7 @@ module t_clk (/*AUTOARG*/
|
||||||
// surefire lint_off STMINI
|
// surefire lint_off STMINI
|
||||||
// surefire lint_off CWECSB
|
// surefire lint_off CWECSB
|
||||||
// surefire lint_off NBAJAM
|
// surefire lint_off NBAJAM
|
||||||
reg _ranit; initial _ranit=0;
|
reg _ranit; initial _ranit=0;
|
||||||
// surefire lint_off UDDSMX
|
// surefire lint_off UDDSMX
|
||||||
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
|
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
|
||||||
wire [7:0] clk_clocks_d1r;
|
wire [7:0] clk_clocks_d1r;
|
||||||
|
|
@ -53,8 +53,8 @@ module t_clk (/*AUTOARG*/
|
||||||
reg [7:0] int_clocks_copy;
|
reg [7:0] int_clocks_copy;
|
||||||
|
|
||||||
// verilator lint_off GENCLK
|
// verilator lint_off GENCLK
|
||||||
reg internal_clk; initial internal_clk = 0;
|
reg internal_clk; initial internal_clk = 0;
|
||||||
reg reset_int_;
|
reg reset_int_;
|
||||||
// verilator lint_on GENCLK
|
// verilator lint_on GENCLK
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
|
|
@ -62,20 +62,20 @@ module t_clk (/*AUTOARG*/
|
||||||
$write("[%0t] CLK1 %x\n", $time, reset_l);
|
$write("[%0t] CLK1 %x\n", $time, reset_l);
|
||||||
`endif
|
`endif
|
||||||
if (!reset_l) begin
|
if (!reset_l) begin
|
||||||
clk_clocks <= 0;
|
clk_clocks <= 0;
|
||||||
int_clocks <= 0;
|
int_clocks <= 0;
|
||||||
internal_clk <= 1'b1;
|
internal_clk <= 1'b1;
|
||||||
reset_int_ <= 0;
|
reset_int_ <= 0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
internal_clk <= ~internal_clk;
|
internal_clk <= ~internal_clk;
|
||||||
if (!_ranit) begin
|
if (!_ranit) begin
|
||||||
_ranit <= 1;
|
_ranit <= 1;
|
||||||
`ifdef TEST_VERBOSE
|
`ifdef TEST_VERBOSE
|
||||||
$write("[%0t] t_clk: Running\n", $time);
|
$write("[%0t] t_clk: Running\n", $time);
|
||||||
`endif
|
`endif
|
||||||
reset_int_ <= 1;
|
reset_int_ <= 1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -85,10 +85,10 @@ module t_clk (/*AUTOARG*/
|
||||||
$write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
|
$write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
|
||||||
`endif
|
`endif
|
||||||
if (!reset_l) begin
|
if (!reset_l) begin
|
||||||
sig_rst <= 0;
|
sig_rst <= 0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
|
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -97,20 +97,20 @@ module t_clk (/*AUTOARG*/
|
||||||
$write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
|
$write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
|
||||||
`endif
|
`endif
|
||||||
if (!reset_l) begin
|
if (!reset_l) begin
|
||||||
clk_clocks <= 0;
|
clk_clocks <= 0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
clk_clocks <= clk_clocks + 8'd1;
|
clk_clocks <= clk_clocks + 8'd1;
|
||||||
if (clk_clocks == 4) begin
|
if (clk_clocks == 4) begin
|
||||||
if (sig_rst !== 4) $stop;
|
if (sig_rst !== 4) $stop;
|
||||||
if (clk_clocks_d1r !== 3) $stop;
|
if (clk_clocks_d1r !== 3) $stop;
|
||||||
if (int_clocks !== 2) $stop;
|
if (int_clocks !== 2) $stop;
|
||||||
if (int_clocks_copy !== 2) $stop;
|
if (int_clocks_copy !== 2) $stop;
|
||||||
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
|
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
|
||||||
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
|
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -120,10 +120,10 @@ module t_clk (/*AUTOARG*/
|
||||||
$write("[%0t] CLK4 %x\n", $time, reset_l);
|
$write("[%0t] CLK4 %x\n", $time, reset_l);
|
||||||
`endif
|
`endif
|
||||||
if (!reset_int_) begin
|
if (!reset_int_) begin
|
||||||
resetted <= 0;
|
resetted <= 0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
resetted <= resetted + 8'd1;
|
resetted <= resetted + 8'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -136,13 +136,13 @@ module t_clk (/*AUTOARG*/
|
||||||
end
|
end
|
||||||
|
|
||||||
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
|
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
|
||||||
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
|
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
|
||||||
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
|
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
|
||||||
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
|
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
|
||||||
t_clk_two two (/*AUTOINST*/
|
t_clk_two two (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.fastclk (fastclk),
|
.fastclk (fastclk),
|
||||||
.reset_l (reset_l));
|
.reset_l (reset_l));
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -17,8 +17,8 @@ module t(/*AUTOARG*/
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc == 99) begin
|
if (cyc == 99) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,28 +10,28 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
reg reset;
|
reg reset;
|
||||||
reg enable;
|
reg enable;
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [31:0] out; // From test of Test.v
|
wire [31:0] out; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire [31:0] in = crc[31:0];
|
wire [31:0] in = crc[31:0];
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out (out[31:0]),
|
.out (out[31:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.reset (reset),
|
.reset (reset),
|
||||||
.enable (enable),
|
.enable (enable),
|
||||||
.in (in[31:0]));
|
.in (in[31:0]));
|
||||||
|
|
||||||
wire [63:0] result = {32'h0, out};
|
wire [63:0] result = {32'h0, out};
|
||||||
|
|
||||||
|
|
@ -46,21 +46,21 @@ module t (/*AUTOARG*/
|
||||||
reset <= (cyc < 5);
|
reset <= (cyc < 5);
|
||||||
enable <= cyc[4] || (cyc < 2);
|
enable <= cyc[4] || (cyc < 2);
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
`define EXPECTED_SUM 64'h01e1553da1dcf3af
|
`define EXPECTED_SUM 64'h01e1553da1dcf3af
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -81,7 +81,7 @@ module Test (/*AUTOARG*/
|
||||||
|
|
||||||
|
|
||||||
// No gating
|
// No gating
|
||||||
reg [31:0] d10;
|
reg [31:0] d10;
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
d10 <= in;
|
d10 <= in;
|
||||||
end
|
end
|
||||||
|
|
@ -94,46 +94,46 @@ module Test (/*AUTOARG*/
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
// Obvious gating + PLI
|
// Obvious gating + PLI
|
||||||
reg [31:0] d20;
|
reg [31:0] d20;
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (enable) begin
|
if (enable) begin
|
||||||
d20 <= d10; // Obvious gating
|
d20 <= d10; // Obvious gating
|
||||||
if (displayit) begin
|
if (displayit) begin
|
||||||
$display("hello!"); // Must glob with other PLI statements
|
$display("hello!"); // Must glob with other PLI statements
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// Reset means second-level gating
|
// Reset means second-level gating
|
||||||
reg [31:0] d30, d31a, d31b, d32;
|
reg [31:0] d30, d31a, d31b, d32;
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
d32 <= d31b;
|
d32 <= d31b;
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
d30 <= 32'h0;
|
d30 <= 32'h0;
|
||||||
d31a <= 32'h0;
|
d31a <= 32'h0;
|
||||||
d31b <= 32'h0;
|
d31b <= 32'h0;
|
||||||
d32 <= 32'h0; // Overlaps above, just to make things interesting
|
d32 <= 32'h0; // Overlaps above, just to make things interesting
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
// Mix two outputs
|
// Mix two outputs
|
||||||
d30 <= d20;
|
d30 <= d20;
|
||||||
if (enable) begin
|
if (enable) begin
|
||||||
d31a <= d30;
|
d31a <= d30;
|
||||||
d31b <= d31a;
|
d31b <= d31a;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// Multiple ORs for gater
|
// Multiple ORs for gater
|
||||||
reg [31:0] d40a,d40b;
|
reg [31:0] d40a,d40b;
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
d40a <= 32'h0;
|
d40a <= 32'h0;
|
||||||
d40b <= 32'h0;
|
d40b <= 32'h0;
|
||||||
end
|
end
|
||||||
if (enable) begin
|
if (enable) begin
|
||||||
d40a <= d32;
|
d40a <= d32;
|
||||||
d40b <= d40a;
|
d40b <= d40a;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -143,15 +143,15 @@ module Test (/*AUTOARG*/
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
inverted = ~d40b;
|
inverted = ~d40b;
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
d91 <= 32'h0;
|
d91 <= 32'h0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if (enable) begin
|
if (enable) begin
|
||||||
d91 <= inverted;
|
d91 <= inverted;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
|
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -13,11 +13,11 @@ module t (/*AUTOARG*/
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
|
|
||||||
// verilator lint_off GENCLK
|
// verilator lint_off GENCLK
|
||||||
reg gendlyclk_r;
|
reg gendlyclk_r;
|
||||||
reg [31:0] gendlydata_r;
|
reg [31:0] gendlydata_r;
|
||||||
reg [31:0] dlydata_gr;
|
reg [31:0] dlydata_gr;
|
||||||
|
|
||||||
reg genblkclk;
|
reg genblkclk;
|
||||||
reg [31:0] genblkdata;
|
reg [31:0] genblkdata;
|
||||||
reg [31:0] blkdata_gr;
|
reg [31:0] blkdata_gr;
|
||||||
|
|
||||||
|
|
@ -27,7 +27,7 @@ module t (/*AUTOARG*/
|
||||||
integer i;
|
integer i;
|
||||||
initial begin
|
initial begin
|
||||||
for (i=0; i<10000; i=i+1) begin
|
for (i=0; i<10000; i=i+1) begin
|
||||||
initwire = 32'h2200;
|
initwire = 32'h2200;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -41,46 +41,46 @@ module t (/*AUTOARG*/
|
||||||
genblkclk = 0;
|
genblkclk = 0;
|
||||||
genblkdata = 0;
|
genblkdata = 0;
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
gendlyclk_r <= 1;
|
gendlyclk_r <= 1;
|
||||||
gendlydata_r <= 32'h00540000;
|
gendlydata_r <= 32'h00540000;
|
||||||
genblkclk = 1;
|
genblkclk = 1;
|
||||||
genblkdata = 32'hace;
|
genblkdata = 32'hace;
|
||||||
$write("[%0t] Send pulse\n", $time);
|
$write("[%0t] Send pulse\n", $time);
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
genblkdata = 32'hdce;
|
genblkdata = 32'hdce;
|
||||||
gendlydata_r <= 32'h00ff0000;
|
gendlydata_r <= 32'h00ff0000;
|
||||||
if (either != 32'h87542211) $stop;
|
if (either != 32'h87542211) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
// surefire lint_on SEQASS
|
// surefire lint_on SEQASS
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (posedge gendlyclk_r) begin
|
always @ (posedge gendlyclk_r) begin
|
||||||
if ($time>0) begin // Hack, don't split the block
|
if ($time>0) begin // Hack, don't split the block
|
||||||
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
|
$write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
|
||||||
dlydata_gr <= 32'h80000000;
|
dlydata_gr <= 32'h80000000;
|
||||||
// Delayed activity list will already be completed for gendlydata
|
// Delayed activity list will already be completed for gendlydata
|
||||||
// because genclk is from a delayed assignment.
|
// because genclk is from a delayed assignment.
|
||||||
// Thus we get the NEW not old value of gendlydata_r
|
// Thus we get the NEW not old value of gendlydata_r
|
||||||
if (gendlydata_r != 32'h00540000) $stop;
|
if (gendlydata_r != 32'h00540000) $stop;
|
||||||
if (genblkdata != 32'hace) $stop;
|
if (genblkdata != 32'hace) $stop;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (posedge genblkclk) begin
|
always @ (posedge genblkclk) begin
|
||||||
if ($time>0) begin // Hack, don't split the block
|
if ($time>0) begin // Hack, don't split the block
|
||||||
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
|
$write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata);
|
||||||
blkdata_gr <= 32'h07000000;
|
blkdata_gr <= 32'h07000000;
|
||||||
// Clock from non-delayed assignment, we get old value of gendlydata_r
|
// Clock from non-delayed assignment, we get old value of gendlydata_r
|
||||||
`ifdef verilator `else // V3.2 races... technically legal
|
`ifdef verilator `else // V3.2 races... technically legal
|
||||||
if (gendlydata_r != 32'h00110000) $stop;
|
if (gendlydata_r != 32'h00110000) $stop;
|
||||||
`endif
|
`endif
|
||||||
if (genblkdata != 32'hace) $stop;
|
if (genblkdata != 32'hace) $stop;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -9,7 +9,7 @@ module t (/*AUTOARG*/
|
||||||
fastclk, clk
|
fastclk, clk
|
||||||
);
|
);
|
||||||
|
|
||||||
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
|
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
|
||||||
`define posstyle posedge
|
`define posstyle posedge
|
||||||
`define negstyle negedge
|
`define negstyle negedge
|
||||||
`else
|
`else
|
||||||
|
|
@ -56,27 +56,27 @@ module t (/*AUTOARG*/
|
||||||
// verilator lint_off LATCH
|
// verilator lint_off LATCH
|
||||||
always @ (`posstyle clk /*AS*/ or data) begin
|
always @ (`posstyle clk /*AS*/ or data) begin
|
||||||
if (clk) begin
|
if (clk) begin
|
||||||
data_a <= data + 8'd1;
|
data_a <= data + 8'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (`posstyle clk /*AS*/ or data_a) begin
|
always @ (`posstyle clk /*AS*/ or data_a) begin
|
||||||
if (clk) begin
|
if (clk) begin
|
||||||
data_a_a <= data_a + 8'd1;
|
data_a_a <= data_a + 8'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (`posstyle clk /*AS*/ or data_b) begin
|
always @ (`posstyle clk /*AS*/ or data_b) begin
|
||||||
if (clk) begin
|
if (clk) begin
|
||||||
data_b_a <= data_b + 8'd1;
|
data_b_a <= data_b + 8'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @ (`negstyle clk /*AS*/ or data or data_a) begin
|
always @ (`negstyle clk /*AS*/ or data or data_a) begin
|
||||||
if (~clk) begin
|
if (~clk) begin
|
||||||
data_b <= data + 8'd1;
|
data_b <= data + 8'd1;
|
||||||
data_a_b <= data_a + 8'd1;
|
data_a_b <= data_a + 8'd1;
|
||||||
data_b_b <= data_b + 8'd1;
|
data_b_b <= data_b + 8'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -88,23 +88,23 @@ module t (/*AUTOARG*/
|
||||||
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
|
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
|
||||||
`endif
|
`endif
|
||||||
if (cyc>=19 && cyc<36) begin
|
if (cyc>=19 && cyc<36) begin
|
||||||
if (compare !== check[cyc]) begin
|
if (compare !== check[cyc]) begin
|
||||||
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
|
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
if (cyc == 10) begin
|
if (cyc == 10) begin
|
||||||
data <= 8'd12;
|
data <= 8'd12;
|
||||||
end
|
end
|
||||||
if (cyc == 20) begin
|
if (cyc == 20) begin
|
||||||
data <= 8'd20;
|
data <= 8'd20;
|
||||||
end
|
end
|
||||||
if (cyc == 30) begin
|
if (cyc == 30) begin
|
||||||
data <= 8'd30;
|
data <= 8'd30;
|
||||||
end
|
end
|
||||||
if (cyc == 40) begin
|
if (cyc == 40) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -28,8 +28,8 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire [7:0] dvld = crc[7:0];
|
wire [7:0] dvld = crc[7:0];
|
||||||
|
|
@ -37,18 +37,18 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [7:0] entry_vld; // From test of Test.v
|
wire [7:0] entry_vld; // From test of Test.v
|
||||||
wire [7:0] ff_en_vld; // From test of Test.v
|
wire [7:0] ff_en_vld; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.ff_en_vld (ff_en_vld[7:0]),
|
.ff_en_vld (ff_en_vld[7:0]),
|
||||||
.entry_vld (entry_vld[7:0]),
|
.entry_vld (entry_vld[7:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.dvld (dvld[7:0]),
|
.dvld (dvld[7:0]),
|
||||||
.ff_en_e1 (ff_en_e1[7:0]));
|
.ff_en_e1 (ff_en_e1[7:0]));
|
||||||
|
|
||||||
reg err_code;
|
reg err_code;
|
||||||
reg ffq_clk_active;
|
reg ffq_clk_active;
|
||||||
|
|
@ -71,16 +71,16 @@ module t (/*AUTOARG*/
|
||||||
`ifdef TEST_VERBOSE
|
`ifdef TEST_VERBOSE
|
||||||
$write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc);
|
$write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc);
|
||||||
$display(" en=%b fen=%b d=%b ev=%b",
|
$display(" en=%b fen=%b d=%b ev=%b",
|
||||||
test.flop_en_vld[0], test.ff_en_vld[0],
|
test.flop_en_vld[0], test.ff_en_vld[0],
|
||||||
test.dvld[0], test.entry_vld[0]);
|
test.dvld[0], test.entry_vld[0]);
|
||||||
`endif
|
`endif
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
if (cyc<3) begin
|
if (cyc<3) begin
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
|
$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc);
|
||||||
if (ffq_clk_active == 0) begin
|
if (ffq_clk_active == 0) begin
|
||||||
$display ("----");
|
$display ("----");
|
||||||
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
|
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
|
||||||
|
|
@ -94,8 +94,8 @@ module t (/*AUTOARG*/
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -11,7 +11,7 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
reg reset_l;
|
reg reset_l;
|
||||||
|
|
||||||
// verilator lint_off GENCLK
|
// verilator lint_off GENCLK
|
||||||
|
|
||||||
|
|
@ -20,13 +20,13 @@ module t (/*AUTOARG*/
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
reg clkgate_e2r;
|
reg clkgate_e2r;
|
||||||
reg clkgate_e1r_l;
|
reg clkgate_e1r_l;
|
||||||
always @(posedge clk or negedge reset_l) begin
|
always @(posedge clk or negedge reset_l) begin
|
||||||
if (!reset_l) begin
|
if (!reset_l) begin
|
||||||
clkgate_e1r_l <= ~1'b1;
|
clkgate_e1r_l <= ~1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
clkgate_e1r_l <= ~clkgate_e2r;
|
clkgate_e1r_l <= ~clkgate_e2r;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -41,20 +41,20 @@ module t (/*AUTOARG*/
|
||||||
reg [31:0] countgated;
|
reg [31:0] countgated;
|
||||||
always @(posedge clkgated or negedge reset_l) begin
|
always @(posedge clkgated or negedge reset_l) begin
|
||||||
if (!reset_l) begin
|
if (!reset_l) begin
|
||||||
countgated <= 32'h1000;
|
countgated <= 32'h1000;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
countgated <= countgated + 32'd1;
|
countgated <= countgated + 32'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
reg [31:0] count;
|
reg [31:0] count;
|
||||||
always @(posedge clk or negedge reset_l) begin
|
always @(posedge clk or negedge reset_l) begin
|
||||||
if (!reset_l) begin
|
if (!reset_l) begin
|
||||||
count <= 32'h1000;
|
count <= 32'h1000;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
count <= count + 32'd1;
|
count <= count + 32'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -65,58 +65,58 @@ module t (/*AUTOARG*/
|
||||||
`endif
|
`endif
|
||||||
cyc <= cyc + 8'd1;
|
cyc <= cyc + 8'd1;
|
||||||
case (cyc)
|
case (cyc)
|
||||||
8'd00: begin
|
8'd00: begin
|
||||||
reset_l <= ~1'b0;
|
reset_l <= ~1'b0;
|
||||||
clkgate_e2r <= 1'b1;
|
clkgate_e2r <= 1'b1;
|
||||||
end
|
end
|
||||||
8'd01: begin
|
8'd01: begin
|
||||||
reset_l <= ~1'b0;
|
reset_l <= ~1'b0;
|
||||||
end
|
end
|
||||||
8'd02: begin
|
8'd02: begin
|
||||||
end
|
end
|
||||||
8'd03: begin
|
8'd03: begin
|
||||||
reset_l <= ~1'b1; // Need a posedge
|
reset_l <= ~1'b1; // Need a posedge
|
||||||
end
|
end
|
||||||
8'd04: begin
|
8'd04: begin
|
||||||
end
|
end
|
||||||
8'd05: begin
|
8'd05: begin
|
||||||
reset_l <= ~1'b0;
|
reset_l <= ~1'b0;
|
||||||
end
|
end
|
||||||
8'd09: begin
|
8'd09: begin
|
||||||
clkgate_e2r <= 1'b0;
|
clkgate_e2r <= 1'b0;
|
||||||
end
|
end
|
||||||
8'd11: begin
|
8'd11: begin
|
||||||
clkgate_e2r <= 1'b1;
|
clkgate_e2r <= 1'b1;
|
||||||
end
|
end
|
||||||
8'd20: begin
|
8'd20: begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
default: ;
|
default: ;
|
||||||
endcase
|
endcase
|
||||||
case (cyc)
|
case (cyc)
|
||||||
8'd00: ;
|
8'd00: ;
|
||||||
8'd01: ;
|
8'd01: ;
|
||||||
8'd02: ;
|
8'd02: ;
|
||||||
8'd03: ;
|
8'd03: ;
|
||||||
8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
|
8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
|
||||||
8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
|
8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
|
||||||
8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
|
8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
|
||||||
8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop;
|
8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop;
|
||||||
8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop;
|
8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop;
|
||||||
8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop;
|
8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop;
|
||||||
8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop;
|
8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop;
|
||||||
8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop;
|
8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop;
|
||||||
8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop;
|
8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop;
|
||||||
8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop;
|
8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop;
|
||||||
8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop;
|
8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop;
|
||||||
8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop;
|
8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop;
|
||||||
8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop;
|
8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop;
|
||||||
8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop;
|
8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop;
|
||||||
8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop;
|
8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop;
|
||||||
8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop;
|
8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop;
|
||||||
8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop;
|
8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop;
|
||||||
default: $stop;
|
default: $stop;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,22 +10,22 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
wire [1:0] clkvec = crc[1:0];
|
wire [1:0] clkvec = crc[1:0];
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [1:0] count; // From test of Test.v
|
wire [1:0] count; // From test of Test.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.count (count[1:0]),
|
.count (count[1:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clkvec (clkvec[1:0]));
|
.clkvec (clkvec[1:0]));
|
||||||
|
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
wire [63:0] result = {62'h0, count};
|
wire [63:0] result = {62'h0, count};
|
||||||
|
|
@ -39,21 +39,21 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
|
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -67,12 +67,12 @@ module Test
|
||||||
output reg [1:0] count
|
output reg [1:0] count
|
||||||
// verilator lint_on MULTIDRIVEN
|
// verilator lint_on MULTIDRIVEN
|
||||||
);
|
);
|
||||||
genvar igen;
|
genvar igen;
|
||||||
generate
|
generate
|
||||||
for (igen=0; igen<2; igen=igen+1) begin : code_gen
|
for (igen=0; igen<2; igen=igen+1) begin : code_gen
|
||||||
initial count[igen] = 1'b0;
|
initial count[igen] = 1'b0;
|
||||||
always @ (posedge clkvec[igen])
|
always @ (posedge clkvec[igen])
|
||||||
count[igen] <= count[igen] + 1;
|
count[igen] <= count[igen] + 1;
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
always @ (count) begin
|
always @ (count) begin
|
||||||
|
|
@ -89,15 +89,15 @@ module Test
|
||||||
output reg [1:0] count
|
output reg [1:0] count
|
||||||
// verilator lint_on MULTIDRIVEN
|
// verilator lint_on MULTIDRIVEN
|
||||||
);
|
);
|
||||||
genvar igen;
|
genvar igen;
|
||||||
generate
|
generate
|
||||||
for (igen=0; igen<2; igen=igen+1) begin : code_gen
|
for (igen=0; igen<2; igen=igen+1) begin : code_gen
|
||||||
wire clk_tmp = clkvec[igen];
|
wire clk_tmp = clkvec[igen];
|
||||||
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
|
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
|
||||||
// need to be.
|
// need to be.
|
||||||
initial count[igen] = 1'b0;
|
initial count[igen] = 1'b0;
|
||||||
always @ (posedge clk_tmp)
|
always @ (posedge clk_tmp)
|
||||||
count[igen] <= count[igen] + 1;
|
count[igen] <= count[igen] + 1;
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
endmodule
|
endmodule
|
||||||
|
|
@ -112,12 +112,12 @@ module Test
|
||||||
genvar igen;
|
genvar igen;
|
||||||
generate
|
generate
|
||||||
for (igen=0; igen<2; igen=igen+1) begin : code_gen
|
for (igen=0; igen<2; igen=igen+1) begin : code_gen
|
||||||
wire clk_tmp = clkvec[igen];
|
wire clk_tmp = clkvec[igen];
|
||||||
reg tmp_count = 1'b0;
|
reg tmp_count = 1'b0;
|
||||||
always @ (posedge clk_tmp) begin
|
always @ (posedge clk_tmp) begin
|
||||||
tmp_count <= tmp_count + 1;
|
tmp_count <= tmp_count + 1;
|
||||||
end
|
end
|
||||||
assign count[igen] = tmp_count;
|
assign count[igen] = tmp_count;
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -56,8 +56,8 @@ module t (/*AUTOARG*/
|
||||||
// because CLOCK signal is used as DATA in sequential block
|
// because CLOCK signal is used as DATA in sequential block
|
||||||
res <= clk_final;
|
res <= clk_final;
|
||||||
if ( count == 8'hf) begin
|
if ( count == 8'hf) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -40,7 +40,7 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
in_a <= cyc;
|
in_a <= cyc;
|
||||||
in_b <= cyc + 1;
|
in_b <= cyc + 1;
|
||||||
in_c <= cyc + 3;
|
in_c <= cyc + 3;
|
||||||
|
|
@ -61,10 +61,10 @@ module t (/*AUTOARG*/
|
||||||
if (out_q != (in_a ^ in_g))
|
if (out_q != (in_a ^ in_g))
|
||||||
$stop;
|
$stop;
|
||||||
|
|
||||||
if (cyc==100) begin
|
if (cyc==100) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,35 +10,35 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
reg toggle;
|
reg toggle;
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
|
|
||||||
Test suba (/*AUTOINST*/
|
Test suba (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle (toggle),
|
.toggle (toggle),
|
||||||
.cyc (cyc[31:0]));
|
.cyc (cyc[31:0]));
|
||||||
Test subb (/*AUTOINST*/
|
Test subb (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle (toggle),
|
.toggle (toggle),
|
||||||
.cyc (cyc[31:0]));
|
.cyc (cyc[31:0]));
|
||||||
Test subc (/*AUTOINST*/
|
Test subc (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle (toggle),
|
.toggle (toggle),
|
||||||
.cyc (cyc[31:0]));
|
.cyc (cyc[31:0]));
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
toggle <= !cyc[0];
|
toggle <= !cyc[0];
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
end
|
end
|
||||||
if (cyc==10) begin
|
if (cyc==10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -17,13 +17,13 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
typedef struct packed {
|
typedef struct packed {
|
||||||
union packed {
|
union packed {
|
||||||
logic ua;
|
logic ua;
|
||||||
logic ub;
|
logic ub;
|
||||||
} u;
|
} u;
|
||||||
logic b;
|
logic b;
|
||||||
} str_t;
|
} str_t;
|
||||||
|
|
||||||
reg toggle; initial toggle='0;
|
reg toggle; initial toggle='0;
|
||||||
|
|
||||||
str_t stoggle; initial stoggle='0;
|
str_t stoggle; initial stoggle='0;
|
||||||
|
|
||||||
|
|
@ -36,29 +36,29 @@ module t (/*AUTOARG*/
|
||||||
wire toggle_up;
|
wire toggle_up;
|
||||||
|
|
||||||
alpha a1 (/*AUTOINST*/
|
alpha a1 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.toggle_up (toggle_up),
|
.toggle_up (toggle_up),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle (toggle),
|
.toggle (toggle),
|
||||||
.cyc_copy (cyc_copy[7:0]));
|
.cyc_copy (cyc_copy[7:0]));
|
||||||
alpha a2 (/*AUTOINST*/
|
alpha a2 (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.toggle_up (toggle_up),
|
.toggle_up (toggle_up),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle (toggle),
|
.toggle (toggle),
|
||||||
.cyc_copy (cyc_copy[7:0]));
|
.cyc_copy (cyc_copy[7:0]));
|
||||||
|
|
||||||
beta b1 (/*AUTOINST*/
|
beta b1 (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle_up (toggle_up));
|
.toggle_up (toggle_up));
|
||||||
|
|
||||||
off o1 (/*AUTOINST*/
|
off o1 (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.toggle (toggle));
|
.toggle (toggle));
|
||||||
|
|
||||||
reg [1:0] memory[121:110];
|
reg [1:0] memory[121:110];
|
||||||
|
|
||||||
|
|
@ -67,22 +67,22 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
|
memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
|
||||||
toggle <= '0;
|
toggle <= '0;
|
||||||
stoggle.u <= toggle;
|
stoggle.u <= toggle;
|
||||||
stoggle.b <= toggle;
|
stoggle.b <= toggle;
|
||||||
ptoggle[0][0] <= toggle;
|
ptoggle[0][0] <= toggle;
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
toggle <= '1;
|
toggle <= '1;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
toggle <= '0;
|
toggle <= '0;
|
||||||
end
|
end
|
||||||
else if (cyc==10) begin
|
else if (cyc==10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -113,7 +113,7 @@ module alpha (/*AUTOARG*/
|
||||||
// CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
|
// CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
|
||||||
// CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
|
// CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
|
||||||
|
|
||||||
reg toggle_internal;
|
reg toggle_internal;
|
||||||
// CHECK_COVER(-1,"top.t.a*",4)
|
// CHECK_COVER(-1,"top.t.a*",4)
|
||||||
// 2 edges * (t.a1 and t.a2)
|
// 2 edges * (t.a1 and t.a2)
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -16,7 +16,7 @@ module t (/*AUTOARG*/
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
typedef struct packed {
|
typedef struct packed {
|
||||||
logic [ID_MSB:0] id;
|
logic [ID_MSB:0] id;
|
||||||
} context_t;
|
} context_t;
|
||||||
|
|
||||||
context_t tsb;
|
context_t tsb;
|
||||||
|
|
@ -34,8 +34,8 @@ module t (/*AUTOARG*/
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
if (tsb.id[1] != 0) begin
|
if (tsb.id[1] != 0) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -18,7 +18,7 @@ module t (/*AUTOARG*/
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
typedef struct packed {
|
typedef struct packed {
|
||||||
logic [1:0] id;
|
logic [1:0] id;
|
||||||
} context_t;
|
} context_t;
|
||||||
|
|
||||||
context_t tsb;
|
context_t tsb;
|
||||||
|
|
@ -36,8 +36,8 @@ module t (/*AUTOARG*/
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
if (tsb.id[1] != 0) begin
|
if (tsb.id[1] != 0) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -32,8 +32,8 @@ module t (/*AUTOARG*/
|
||||||
always @(posedge clk or negedge clk) begin
|
always @(posedge clk or negedge clk) begin
|
||||||
|
|
||||||
if (res != 0) begin
|
if (res != 0) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -56,13 +56,13 @@ module test_sub (/*AUTOARG*/
|
||||||
|
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer i; // General counter
|
integer i; // General counter
|
||||||
|
|
||||||
// Elements we would like to access from outside
|
// Elements we would like to access from outside
|
||||||
reg a;
|
reg a;
|
||||||
reg [`REG_WIDTH - 1:0] b;
|
reg [`REG_WIDTH - 1:0] b;
|
||||||
reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0];
|
reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0];
|
||||||
wire c;
|
wire c;
|
||||||
wire [`REG_WIDTH - 1:0] d;
|
wire [`REG_WIDTH - 1:0] d;
|
||||||
reg [`REG_WIDTH - 1:0] e;
|
reg [`REG_WIDTH - 1:0] e;
|
||||||
reg [`REG_WIDTH - 1:0] f;
|
reg [`REG_WIDTH - 1:0] f;
|
||||||
|
|
@ -77,7 +77,7 @@ module test_sub (/*AUTOARG*/
|
||||||
b = `REG_WIDTH'h0;
|
b = `REG_WIDTH'h0;
|
||||||
|
|
||||||
for (i = 0; i < `MEM_SIZE; i++) begin
|
for (i = 0; i < `MEM_SIZE; i++) begin
|
||||||
mem[i] = i [`REG_WIDTH - 1:0];
|
mem[i] = i [`REG_WIDTH - 1:0];
|
||||||
end
|
end
|
||||||
|
|
||||||
e = 0;
|
e = 0;
|
||||||
|
|
|
||||||
|
|
@ -17,12 +17,12 @@ module t (/*AUTOARG*/
|
||||||
generate
|
generate
|
||||||
for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice
|
for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice
|
||||||
|
|
||||||
import "DPI-C" context function void dpi_genvarTest ();
|
import "DPI-C" context function void dpi_genvarTest ();
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
dpi_genvarTest();
|
dpi_genvarTest();
|
||||||
$display("slice = %0d : %m", blkIdx);
|
$display("slice = %0d : %m", blkIdx);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -32,7 +32,7 @@ module t (/*AUTOARG*/
|
||||||
// Scalar bit and logic
|
// Scalar bit and logic
|
||||||
//
|
//
|
||||||
// Allowed argument types:
|
// Allowed argument types:
|
||||||
// Same as above plus packed arrays
|
// Same as above plus packed arrays
|
||||||
|
|
||||||
import "DPI-C" pure function bit dpii_f_bit (input bit i);
|
import "DPI-C" pure function bit dpii_f_bit (input bit i);
|
||||||
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
|
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
|
||||||
|
|
@ -42,7 +42,7 @@ module t (/*AUTOARG*/
|
||||||
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
|
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
|
||||||
// Illegal to return > 32 bits, so we use longint
|
// Illegal to return > 32 bits, so we use longint
|
||||||
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
|
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
|
||||||
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
|
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
|
||||||
import "DPI-C" pure function int dpii_f_int (input int i);
|
import "DPI-C" pure function int dpii_f_int (input int i);
|
||||||
import "DPI-C" pure function byte dpii_f_byte (input byte i);
|
import "DPI-C" pure function byte dpii_f_byte (input byte i);
|
||||||
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
|
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
|
||||||
|
|
@ -97,34 +97,34 @@ module t (/*AUTOARG*/
|
||||||
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
|
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
|
||||||
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
|
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
|
||||||
|
|
||||||
bit i_b, o_b;
|
bit i_b, o_b;
|
||||||
bit [7:0] i_b8;
|
bit [7:0] i_b8;
|
||||||
bit [8:0] i_b9;
|
bit [8:0] i_b9;
|
||||||
bit [15:0] i_b16;
|
bit [15:0] i_b16;
|
||||||
bit [16:0] i_b17;
|
bit [16:0] i_b17;
|
||||||
bit [31:0] i_b32;
|
bit [31:0] i_b32;
|
||||||
bit [32:0] i_b33, o_b33;
|
bit [32:0] i_b33, o_b33;
|
||||||
bit [63:0] i_b64, o_b64;
|
bit [63:0] i_b64, o_b64;
|
||||||
bit [94:0] i_b95, o_b95;
|
bit [94:0] i_b95, o_b95;
|
||||||
bit [95:0] i_b96, o_b96;
|
bit [95:0] i_b96, o_b96;
|
||||||
|
|
||||||
int i_i, o_i;
|
int i_i, o_i;
|
||||||
byte i_y, o_y;
|
byte i_y, o_y;
|
||||||
shortint i_s, o_s;
|
shortint i_s, o_s;
|
||||||
longint i_l, o_l;
|
longint i_l, o_l;
|
||||||
str_t i_t, o_t;
|
str_t i_t, o_t;
|
||||||
substr_t i_ss;
|
substr_t i_ss;
|
||||||
int o_ss;
|
int o_ss;
|
||||||
int unsigned i_iu, o_iu;
|
int unsigned i_iu, o_iu;
|
||||||
shortint unsigned i_su, o_su;
|
shortint unsigned i_su, o_su;
|
||||||
longint unsigned i_lu, o_lu;
|
longint unsigned i_lu, o_lu;
|
||||||
// verilator lint_off UNDRIVEN
|
// verilator lint_off UNDRIVEN
|
||||||
chandle i_c, o_c;
|
chandle i_c, o_c;
|
||||||
string i_n, o_n;
|
string i_n, o_n;
|
||||||
// verilator lint_on UNDRIVEN
|
// verilator lint_on UNDRIVEN
|
||||||
real i_d, o_d;
|
real i_d, o_d;
|
||||||
`ifndef NO_SHORTREAL
|
`ifndef NO_SHORTREAL
|
||||||
shortreal i_f, o_f;
|
shortreal i_f, o_f;
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
reg i_r, o_r;
|
reg i_r, o_r;
|
||||||
|
|
|
||||||
|
|
@ -17,8 +17,8 @@ module t;
|
||||||
initial begin
|
initial begin
|
||||||
poke_value(32'hdeadbeef);
|
poke_value(32'hdeadbeef);
|
||||||
if (out !== 40'hdeadbeef) begin
|
if (out !== 40'hdeadbeef) begin
|
||||||
$display("[%0t] %%Error: t_dpi_qw: failed", $time);
|
$display("[%0t] %%Error: t_dpi_qw: failed", $time);
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end
|
||||||
|
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
|
|
|
||||||
|
|
@ -27,19 +27,19 @@ module t (/*AUTOARG*/);
|
||||||
|
|
||||||
integer i;
|
integer i;
|
||||||
integer j;
|
integer j;
|
||||||
bit b;
|
bit b;
|
||||||
integer errors;
|
integer errors;
|
||||||
|
|
||||||
task check1(integer line, bit got, bit ex);
|
task check1(integer line, bit got, bit ex);
|
||||||
if (got != ex) begin
|
if (got != ex) begin
|
||||||
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
||||||
errors++;
|
errors++;
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
task check(integer line, int got, int ex);
|
task check(integer line, int got, int ex);
|
||||||
if (got != ex) begin
|
if (got != ex) begin
|
||||||
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
||||||
errors++;
|
errors++;
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
|
|
@ -192,12 +192,12 @@ module t (/*AUTOARG*/);
|
||||||
// Something a lot more complicated
|
// Something a lot more complicated
|
||||||
dpii_clear();
|
dpii_clear();
|
||||||
for (i=0; i<64; i++) begin
|
for (i=0; i<64; i++) begin
|
||||||
b = ( ((dpii_incx(0,i[0])
|
b = ( ((dpii_incx(0,i[0])
|
||||||
&& (dpii_incx(1,i[1])
|
&& (dpii_incx(1,i[1])
|
||||||
|| dpii_incx(2,i[2])
|
|| dpii_incx(2,i[2])
|
||||||
| dpii_incx(3,i[3]))) // | not ||
|
| dpii_incx(3,i[3]))) // | not ||
|
||||||
|| dpii_incx(4,i[4]))
|
|| dpii_incx(4,i[4]))
|
||||||
-> dpii_incx(5,i[5]));
|
-> dpii_incx(5,i[5]));
|
||||||
end
|
end
|
||||||
check (`__LINE__, dpii_count(0), 64);
|
check (`__LINE__, dpii_count(0), 64);
|
||||||
check (`__LINE__, dpii_count(1), 32);
|
check (`__LINE__, dpii_count(1), 32);
|
||||||
|
|
|
||||||
|
|
@ -28,19 +28,19 @@ module t (/*AUTOARG*/);
|
||||||
integer i;
|
integer i;
|
||||||
integer j;
|
integer j;
|
||||||
integer k;
|
integer k;
|
||||||
bit b;
|
bit b;
|
||||||
integer errors;
|
integer errors;
|
||||||
|
|
||||||
task check1(integer line, bit got, bit ex);
|
task check1(integer line, bit got, bit ex);
|
||||||
if (got != ex) begin
|
if (got != ex) begin
|
||||||
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
||||||
errors++;
|
errors++;
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
task check(integer line, int got, int ex);
|
task check(integer line, int got, int ex);
|
||||||
if (got != ex) begin
|
if (got != ex) begin
|
||||||
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
|
||||||
errors++;
|
errors++;
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
|
|
@ -52,11 +52,11 @@ module t (/*AUTOARG*/);
|
||||||
// verilator lint_on IGNOREDRETURN
|
// verilator lint_on IGNOREDRETURN
|
||||||
j = 0;
|
j = 0;
|
||||||
for (i=0; i<64; i++) begin
|
for (i=0; i<64; i++) begin
|
||||||
if (i[0])
|
if (i[0])
|
||||||
j = 0;
|
j = 0;
|
||||||
else
|
else
|
||||||
j = {31'b0, dpii_inc1(0)};
|
j = {31'b0, dpii_inc1(0)};
|
||||||
k = k + j;
|
k = k + j;
|
||||||
end
|
end
|
||||||
$write("%x\n",k);
|
$write("%x\n",k);
|
||||||
check (`__LINE__, dpii_count(0), 32);
|
check (`__LINE__, dpii_count(0), 32);
|
||||||
|
|
|
||||||
|
|
@ -16,10 +16,10 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
wire monclk = ~clk;
|
wire monclk = ~clk;
|
||||||
|
|
||||||
int in;
|
int in;
|
||||||
int fr_a;
|
int fr_a;
|
||||||
int fr_b;
|
int fr_b;
|
||||||
int fr_chk;
|
int fr_chk;
|
||||||
sub sub (.*);
|
sub sub (.*);
|
||||||
|
|
||||||
// Test loop
|
// Test loop
|
||||||
|
|
@ -30,18 +30,18 @@ module t (/*AUTOARG*/
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
in <= {in[30:0], in[31]^in[2]^in[0]};
|
in <= {in[30:0], in[31]^in[2]^in[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
in <= 32'hd70a4497;
|
in <= 32'hd70a4497;
|
||||||
end
|
end
|
||||||
else if (cyc<3) begin
|
else if (cyc<3) begin
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
if (fr_chk != fr_a) $stop;
|
if (fr_chk != fr_a) $stop;
|
||||||
if (fr_chk != fr_b) $stop;
|
if (fr_chk != fr_b) $stop;
|
||||||
end
|
end
|
||||||
else if (cyc==10) begin
|
else if (cyc==10) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,9 +10,9 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire bit_in = crc[0];
|
wire bit_in = crc[0];
|
||||||
|
|
@ -21,14 +21,14 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire exp_bit_out; // From reference of t_embed1_child.v
|
wire exp_bit_out; // From reference of t_embed1_child.v
|
||||||
wire exp_did_init_out; // From reference of t_embed1_child.v
|
wire exp_did_init_out; // From reference of t_embed1_child.v
|
||||||
wire [30:0] exp_vec_out; // From reference of t_embed1_child.v
|
wire [30:0] exp_vec_out; // From reference of t_embed1_child.v
|
||||||
wire [123:0] exp_wide_out; // From reference of t_embed1_child.v
|
wire [123:0] exp_wide_out; // From reference of t_embed1_child.v
|
||||||
wire got_bit_out; // From test of t_embed1_wrap.v
|
wire got_bit_out; // From test of t_embed1_wrap.v
|
||||||
wire got_did_init_out; // From test of t_embed1_wrap.v
|
wire got_did_init_out; // From test of t_embed1_wrap.v
|
||||||
wire [30:0] got_vec_out; // From test of t_embed1_wrap.v
|
wire [30:0] got_vec_out; // From test of t_embed1_wrap.v
|
||||||
wire [123:0] got_wide_out; // From test of t_embed1_wrap.v
|
wire [123:0] got_wide_out; // From test of t_embed1_wrap.v
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
// A non-embedded master
|
// A non-embedded master
|
||||||
|
|
@ -40,16 +40,16 @@ module t (/*AUTOARG*/
|
||||||
t_embed1_child reference
|
t_embed1_child reference
|
||||||
(/*AUTOINST*/
|
(/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.bit_out (exp_bit_out), // Templated
|
.bit_out (exp_bit_out), // Templated
|
||||||
.vec_out (exp_vec_out[30:0]), // Templated
|
.vec_out (exp_vec_out[30:0]), // Templated
|
||||||
.wide_out (exp_wide_out[123:0]), // Templated
|
.wide_out (exp_wide_out[123:0]), // Templated
|
||||||
.did_init_out (exp_did_init_out), // Templated
|
.did_init_out (exp_did_init_out), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.bit_in (bit_in),
|
.bit_in (bit_in),
|
||||||
.vec_in (vec_in[30:0]),
|
.vec_in (vec_in[30:0]),
|
||||||
.wide_in (wide_in[123:0]),
|
.wide_in (wide_in[123:0]),
|
||||||
.is_ref (1'b1)); // Templated
|
.is_ref (1'b1)); // Templated
|
||||||
|
|
||||||
// The embeded comparison
|
// The embeded comparison
|
||||||
|
|
||||||
|
|
@ -61,49 +61,49 @@ module t (/*AUTOARG*/
|
||||||
t_embed1_wrap test
|
t_embed1_wrap test
|
||||||
(/*AUTOINST*/
|
(/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.bit_out (got_bit_out), // Templated
|
.bit_out (got_bit_out), // Templated
|
||||||
.vec_out (got_vec_out[30:0]), // Templated
|
.vec_out (got_vec_out[30:0]), // Templated
|
||||||
.wide_out (got_wide_out[123:0]), // Templated
|
.wide_out (got_wide_out[123:0]), // Templated
|
||||||
.did_init_out (got_did_init_out), // Templated
|
.did_init_out (got_did_init_out), // Templated
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.bit_in (bit_in),
|
.bit_in (bit_in),
|
||||||
.vec_in (vec_in[30:0]),
|
.vec_in (vec_in[30:0]),
|
||||||
.wide_in (wide_in[123:0]),
|
.wide_in (wide_in[123:0]),
|
||||||
.is_ref (1'b0)); // Templated
|
.is_ref (1'b0)); // Templated
|
||||||
|
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
wire [63:0] result = {60'h0,
|
wire [63:0] result = {60'h0,
|
||||||
got_wide_out !== exp_wide_out,
|
got_wide_out !== exp_wide_out,
|
||||||
got_vec_out !== exp_vec_out,
|
got_vec_out !== exp_vec_out,
|
||||||
got_bit_out !== exp_bit_out,
|
got_bit_out !== exp_bit_out,
|
||||||
got_did_init_out !== exp_did_init_out};
|
got_did_init_out !== exp_did_init_out};
|
||||||
|
|
||||||
// Test loop
|
// Test loop
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
`ifdef TEST_VERBOSE
|
`ifdef TEST_VERBOSE
|
||||||
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result,
|
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result,
|
||||||
got_vec_out, exp_vec_out);
|
got_vec_out, exp_vec_out);
|
||||||
`endif
|
`endif
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
if (result != 64'h0) begin
|
if (result != 64'h0) begin
|
||||||
$display("Bit mismatch, result=%x\n", result);
|
$display("Bit mismatch, result=%x\n", result);
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
//Child prints this: $write("*-* All Finished *-*\n");
|
//Child prints this: $write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -18,9 +18,9 @@ module t_embed1_child (/*AUTOARG*/
|
||||||
output logic [30:0] vec_out;
|
output logic [30:0] vec_out;
|
||||||
input [123:0] wide_in;
|
input [123:0] wide_in;
|
||||||
output logic [123:0] wide_out;
|
output logic [123:0] wide_out;
|
||||||
output did_init_out;
|
output did_init_out;
|
||||||
|
|
||||||
input is_ref;
|
input is_ref;
|
||||||
|
|
||||||
reg did_init; initial did_init = 0;
|
reg did_init; initial did_init = 0;
|
||||||
initial begin
|
initial begin
|
||||||
|
|
|
||||||
|
|
@ -17,11 +17,11 @@ module t_embed1_wrap (/*AUTOARG*/
|
||||||
output bit [30:0] vec_out;
|
output bit [30:0] vec_out;
|
||||||
output bit [123:0] wide_out;
|
output bit [123:0] wide_out;
|
||||||
output bit did_init_out;
|
output bit did_init_out;
|
||||||
input clk;
|
input clk;
|
||||||
input bit_in;
|
input bit_in;
|
||||||
input [30:0] vec_in;
|
input [30:0] vec_in;
|
||||||
input [123:0] wide_in;
|
input [123:0] wide_in;
|
||||||
input is_ref;
|
input is_ref;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
`ifdef verilator
|
`ifdef verilator
|
||||||
|
|
@ -61,16 +61,16 @@ module t_embed1_wrap (/*AUTOARG*/
|
||||||
bit [123:0] _temp_wide_out;
|
bit [123:0] _temp_wide_out;
|
||||||
always @* begin
|
always @* begin
|
||||||
t_embed_child_io_eval(
|
t_embed_child_io_eval(
|
||||||
clk,
|
clk,
|
||||||
bit_in,
|
bit_in,
|
||||||
vec_in,
|
vec_in,
|
||||||
wide_in,
|
wide_in,
|
||||||
is_ref,
|
is_ref,
|
||||||
_temp_bit_out,
|
_temp_bit_out,
|
||||||
_temp_vec_out,
|
_temp_vec_out,
|
||||||
_temp_wide_out,
|
_temp_wide_out,
|
||||||
_temp_did_init_out
|
_temp_did_init_out
|
||||||
);
|
);
|
||||||
// TODO might eliminate these temporaries
|
// TODO might eliminate these temporaries
|
||||||
bit_out = _temp_bit_out;
|
bit_out = _temp_bit_out;
|
||||||
did_init_out = _temp_did_init_out;
|
did_init_out = _temp_did_init_out;
|
||||||
|
|
|
||||||
|
|
@ -12,9 +12,9 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad};
|
bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad};
|
||||||
|
|
||||||
|
|
@ -25,26 +25,26 @@ module t (/*AUTOARG*/
|
||||||
bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199};
|
bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199};
|
||||||
|
|
||||||
bit [9*32-1:0] w9 = {32'hca800ac1,
|
bit [9*32-1:0] w9 = {32'hca800ac1,
|
||||||
32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621};
|
32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621};
|
||||||
|
|
||||||
bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32,
|
bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32,
|
||||||
32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8};
|
32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8};
|
||||||
|
|
||||||
bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e,
|
bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e,
|
||||||
32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784};
|
32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784};
|
||||||
|
|
||||||
bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e,
|
bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e,
|
||||||
32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302};
|
32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302};
|
||||||
|
|
||||||
bit [17*32-1:0] w17 = {32'hf1e322ac,
|
bit [17*32-1:0] w17 = {32'hf1e322ac,
|
||||||
32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23,
|
32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23,
|
||||||
32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1};
|
32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1};
|
||||||
|
|
||||||
function [7:0] bytehash (input [32*32-1:0] data);
|
function [7:0] bytehash (input [32*32-1:0] data);
|
||||||
integer i;
|
integer i;
|
||||||
bytehash = 0;
|
bytehash = 0;
|
||||||
for (i=0; i<32*32; ++i) begin
|
for (i=0; i<32*32; ++i) begin
|
||||||
bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8];
|
bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8];
|
||||||
end
|
end
|
||||||
return bytehash;
|
return bytehash;
|
||||||
endfunction
|
endfunction
|
||||||
|
|
@ -52,14 +52,14 @@ module t (/*AUTOARG*/
|
||||||
// Aggregate outputs into a single result vector
|
// Aggregate outputs into a single result vector
|
||||||
// verilator lint_off WIDTH
|
// verilator lint_off WIDTH
|
||||||
wire [63:0] result = (bytehash(w4)
|
wire [63:0] result = (bytehash(w4)
|
||||||
^ bytehash(w8m)
|
^ bytehash(w8m)
|
||||||
^ bytehash(w8)
|
^ bytehash(w8)
|
||||||
^ bytehash(w8p)
|
^ bytehash(w8p)
|
||||||
^ bytehash(w9)
|
^ bytehash(w9)
|
||||||
^ bytehash(w16m)
|
^ bytehash(w16m)
|
||||||
^ bytehash(w16)
|
^ bytehash(w16)
|
||||||
^ bytehash(w16p)
|
^ bytehash(w16p)
|
||||||
^ bytehash(w17));
|
^ bytehash(w17));
|
||||||
// verilator lint_on WIDTH
|
// verilator lint_on WIDTH
|
||||||
|
|
||||||
`define EXPECTED_SUM 64'h2bc7c2a98a302891
|
`define EXPECTED_SUM 64'h2bc7c2a98a302891
|
||||||
|
|
@ -73,8 +73,8 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
// verilator lint_off SELRANGE
|
// verilator lint_off SELRANGE
|
||||||
`checkhw(w4,3,32'h7c709753);
|
`checkhw(w4,3,32'h7c709753);
|
||||||
`checkhw(w4,2,32'hbc8f6059);
|
`checkhw(w4,2,32'hbc8f6059);
|
||||||
|
|
@ -133,25 +133,25 @@ module t (/*AUTOARG*/
|
||||||
// verilator lint_on SELRANGE
|
// verilator lint_on SELRANGE
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
w4 = w4 >>> 1;
|
w4 = w4 >>> 1;
|
||||||
w8m = w8m >>> 1;
|
w8m = w8m >>> 1;
|
||||||
w8 = w8 >>> 1;
|
w8 = w8 >>> 1;
|
||||||
w8p = w8p >>> 1;
|
w8p = w8p >>> 1;
|
||||||
w9 = w9 >>> 1;
|
w9 = w9 >>> 1;
|
||||||
w16m = w16m >>> 1;
|
w16m = w16m >>> 1;
|
||||||
w16 = w16 >>> 1;
|
w16 = w16 >>> 1;
|
||||||
w16p = w16p >>> 1;
|
w16p = w16p >>> 1;
|
||||||
w17 = w17 >>> 1;
|
w17 = w17 >>> 1;
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -16,20 +16,20 @@ module t (/*AUTOARG*/);
|
||||||
localparam FIVE = 5;
|
localparam FIVE = 5;
|
||||||
|
|
||||||
enum { e0,
|
enum { e0,
|
||||||
e1,
|
e1,
|
||||||
e3=3,
|
e3=3,
|
||||||
e5=FIVE,
|
e5=FIVE,
|
||||||
e10_[2] = 10,
|
e10_[2] = 10,
|
||||||
e12,
|
e12,
|
||||||
e20_[5:7] = 25,
|
e20_[5:7] = 25,
|
||||||
e20_z,
|
e20_z,
|
||||||
e30_[7:5] = 30,
|
e30_[7:5] = 30,
|
||||||
e30_z
|
e30_z
|
||||||
} EN;
|
} EN;
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
z5 = e5
|
z5 = e5
|
||||||
} ZN;
|
} ZN;
|
||||||
|
|
||||||
typedef enum three_t; // Forward
|
typedef enum three_t; // Forward
|
||||||
typedef enum [2:0] { ONES=~0 } three_t;
|
typedef enum [2:0] { ONES=~0 } three_t;
|
||||||
|
|
@ -38,7 +38,7 @@ module t (/*AUTOARG*/);
|
||||||
var logic [ONES:0] sized_based_on_enum;
|
var logic [ONES:0] sized_based_on_enum;
|
||||||
|
|
||||||
var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2},
|
var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2},
|
||||||
QPR={2'b0,2'h3 }, QACK, QRSP } inv;
|
QPR={2'b0,2'h3 }, QACK, QRSP } inv;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
if (e0 !== 0) $stop;
|
if (e0 !== 0) $stop;
|
||||||
|
|
|
||||||
|
|
@ -5,8 +5,8 @@
|
||||||
// SPDX-License-Identifier: CC0-1.0
|
// SPDX-License-Identifier: CC0-1.0
|
||||||
|
|
||||||
typedef enum { EN_ZERO,
|
typedef enum { EN_ZERO,
|
||||||
EN_ONE
|
EN_ONE
|
||||||
} En_t;
|
} En_t;
|
||||||
|
|
||||||
module t (/*AUTOARG*/
|
module t (/*AUTOARG*/
|
||||||
// Inputs
|
// Inputs
|
||||||
|
|
@ -16,9 +16,9 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
// Insure that we can declare a type with a function declaration
|
// Insure that we can declare a type with a function declaration
|
||||||
function enum integer {
|
function enum integer {
|
||||||
EF_TRUE = 1,
|
EF_TRUE = 1,
|
||||||
EF_FALSE = 0 }
|
EF_FALSE = 0 }
|
||||||
f_enum_inv ( input a);
|
f_enum_inv ( input a);
|
||||||
f_enum_inv = a ? EF_FALSE : EF_TRUE;
|
f_enum_inv = a ? EF_FALSE : EF_TRUE;
|
||||||
endfunction
|
endfunction
|
||||||
initial begin
|
initial begin
|
||||||
|
|
@ -29,29 +29,29 @@ module t (/*AUTOARG*/
|
||||||
En_t a, z;
|
En_t a, z;
|
||||||
|
|
||||||
sub sub (/*AUTOINST*/
|
sub sub (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.z (z),
|
.z (z),
|
||||||
// Inputs
|
// Inputs
|
||||||
.a (a));
|
.a (a));
|
||||||
|
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
a <= EN_ZERO;
|
a <= EN_ZERO;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
a <= EN_ONE;
|
a <= EN_ONE;
|
||||||
if (z != EN_ONE) $stop;
|
if (z != EN_ONE) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
if (z != EN_ZERO) $stop;
|
if (z != EN_ZERO) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,9 +1,9 @@
|
||||||
%Error: t/t_enum_huge_methods_bad.v:15:11: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd
|
%Error: t/t_enum_huge_methods_bad.v:15:18: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd
|
||||||
15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
|
15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
|
||||||
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:14: Unsupported: enum next/prev/name method on enum with > 64 bits
|
%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:21: Unsupported: enum next/prev/name method on enum with > 64 bits
|
||||||
: ... In instance t
|
: ... In instance t
|
||||||
30 | $display(e.name);
|
30 | $display(e.name);
|
||||||
| ^~~~
|
| ^~~~
|
||||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||||
%Error: Exiting due to
|
%Error: Exiting due to
|
||||||
|
|
|
||||||
|
|
@ -12,27 +12,27 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
typedef enum logic [159:0] {
|
typedef enum logic [159:0] {
|
||||||
E01 = 160'h1,
|
E01 = 160'h1,
|
||||||
ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
|
ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
|
||||||
} my_t;
|
} my_t;
|
||||||
|
|
||||||
my_t e;
|
my_t e;
|
||||||
|
|
||||||
int cyc;
|
int cyc;
|
||||||
|
|
||||||
// Check runtime
|
// Check runtime
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
e <= E01;
|
e <= E01;
|
||||||
end
|
end
|
||||||
else if (cyc==1) begin
|
else if (cyc==1) begin
|
||||||
$display(e.name);
|
$display(e.name);
|
||||||
e <= ELARGE;
|
e <= ELARGE;
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -13,32 +13,32 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
enum integer {
|
enum integer {
|
||||||
|
|
||||||
EP_State_IDLE ,
|
EP_State_IDLE ,
|
||||||
EP_State_CMDSHIFT0 ,
|
EP_State_CMDSHIFT0 ,
|
||||||
EP_State_CMDSHIFT13 ,
|
EP_State_CMDSHIFT13 ,
|
||||||
EP_State_CMDSHIFT14 ,
|
EP_State_CMDSHIFT14 ,
|
||||||
EP_State_CMDSHIFT15 ,
|
EP_State_CMDSHIFT15 ,
|
||||||
EP_State_CMDSHIFT16 ,
|
EP_State_CMDSHIFT16 ,
|
||||||
EP_State_DWAIT ,
|
EP_State_DWAIT ,
|
||||||
EP_State_DSHIFT0 ,
|
EP_State_DSHIFT0 ,
|
||||||
EP_State_DSHIFT1 ,
|
EP_State_DSHIFT1 ,
|
||||||
EP_State_DSHIFT15 } m_state_xr, m_state2_xr;
|
EP_State_DSHIFT15 } m_state_xr, m_state2_xr;
|
||||||
|
|
||||||
// Beginning of automatic ASCII enum decoding
|
// Beginning of automatic ASCII enum decoding
|
||||||
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
|
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
|
||||||
always @(m_state_xr) begin
|
always @(m_state_xr) begin
|
||||||
case ({m_state_xr})
|
case ({m_state_xr})
|
||||||
EP_State_IDLE: m_stateAscii_xr = "idle ";
|
EP_State_IDLE: m_stateAscii_xr = "idle ";
|
||||||
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
|
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
|
||||||
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
|
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
|
||||||
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
|
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
|
||||||
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
|
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
|
||||||
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
|
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
|
||||||
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
|
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
|
||||||
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
|
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
|
||||||
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
|
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
|
||||||
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
|
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
|
||||||
default: m_stateAscii_xr = "%Error ";
|
default: m_stateAscii_xr = "%Error ";
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
@ -46,36 +46,36 @@ module t (/*AUTOARG*/
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
|
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
m_state_xr <= EP_State_IDLE;
|
m_state_xr <= EP_State_IDLE;
|
||||||
m_state2_xr <= EP_State_IDLE;
|
m_state2_xr <= EP_State_IDLE;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
if (m_stateAscii_xr != "idle ") $stop;
|
if (m_stateAscii_xr != "idle ") $stop;
|
||||||
m_state_xr <= EP_State_CMDSHIFT13;
|
m_state_xr <= EP_State_CMDSHIFT13;
|
||||||
if (m_state2_xr != EP_State_IDLE) $stop;
|
if (m_state2_xr != EP_State_IDLE) $stop;
|
||||||
m_state2_xr <= EP_State_CMDSHIFT13;
|
m_state2_xr <= EP_State_CMDSHIFT13;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
if (m_stateAscii_xr != "cmdshift13") $stop;
|
if (m_stateAscii_xr != "cmdshift13") $stop;
|
||||||
m_state_xr <= EP_State_CMDSHIFT16;
|
m_state_xr <= EP_State_CMDSHIFT16;
|
||||||
if (m_state2_xr != EP_State_CMDSHIFT13) $stop;
|
if (m_state2_xr != EP_State_CMDSHIFT13) $stop;
|
||||||
m_state2_xr <= EP_State_CMDSHIFT16;
|
m_state2_xr <= EP_State_CMDSHIFT16;
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
if (m_stateAscii_xr != "cmdshift16") $stop;
|
if (m_stateAscii_xr != "cmdshift16") $stop;
|
||||||
m_state_xr <= EP_State_DWAIT;
|
m_state_xr <= EP_State_DWAIT;
|
||||||
if (m_state2_xr != EP_State_CMDSHIFT16) $stop;
|
if (m_state2_xr != EP_State_CMDSHIFT16) $stop;
|
||||||
m_state2_xr <= EP_State_DWAIT;
|
m_state2_xr <= EP_State_DWAIT;
|
||||||
end
|
end
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
if (m_stateAscii_xr != "dwait ") $stop;
|
if (m_stateAscii_xr != "dwait ") $stop;
|
||||||
if (m_state2_xr != EP_State_DWAIT) $stop;
|
if (m_state2_xr != EP_State_DWAIT) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -14,11 +14,11 @@ module t (/*AUTOARG*/
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
E01 = 'h1,
|
E01 = 'h1,
|
||||||
ELARGE = 'hf00d
|
ELARGE = 'hf00d
|
||||||
} my_t;
|
} my_t;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
my_t e;
|
my_t e;
|
||||||
|
|
||||||
string all;
|
string all;
|
||||||
|
|
@ -27,29 +27,29 @@ module t (/*AUTOARG*/
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
e <= E01;
|
e <= E01;
|
||||||
end
|
end
|
||||||
else if (cyc==1) begin
|
else if (cyc==1) begin
|
||||||
`checks(e.name, "E01");
|
`checks(e.name, "E01");
|
||||||
`checkh(e.next, ELARGE);
|
`checkh(e.next, ELARGE);
|
||||||
e <= ELARGE;
|
e <= ELARGE;
|
||||||
end
|
end
|
||||||
else if (cyc==3) begin
|
else if (cyc==3) begin
|
||||||
`checks(e.name, "ELARGE");
|
`checks(e.name, "ELARGE");
|
||||||
`checkh(e.next, E01);
|
`checkh(e.next, E01);
|
||||||
`checkh(e.prev, E01);
|
`checkh(e.prev, E01);
|
||||||
e <= E01;
|
e <= E01;
|
||||||
end
|
end
|
||||||
else if (cyc==20) begin
|
else if (cyc==20) begin
|
||||||
e <= my_t'('h11); // Unknown
|
e <= my_t'('h11); // Unknown
|
||||||
end
|
end
|
||||||
else if (cyc==21) begin
|
else if (cyc==21) begin
|
||||||
`checks(e.name, ""); // Unknown
|
`checks(e.name, ""); // Unknown
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -6,11 +6,11 @@
|
||||||
|
|
||||||
package our_pkg;
|
package our_pkg;
|
||||||
typedef enum logic [8-1:0] {
|
typedef enum logic [8-1:0] {
|
||||||
ADC_IN2IN = 8'h99,
|
ADC_IN2IN = 8'h99,
|
||||||
ADC_IMMED = 8'h88,
|
ADC_IMMED = 8'h88,
|
||||||
ADC_INDIR = 8'h86,
|
ADC_INDIR = 8'h86,
|
||||||
ADC_INIDX = 8'h97
|
ADC_INIDX = 8'h97
|
||||||
} T_Opcode;
|
} T_Opcode;
|
||||||
endpackage : our_pkg
|
endpackage : our_pkg
|
||||||
|
|
||||||
module t ();
|
module t ();
|
||||||
|
|
|
||||||
|
|
@ -22,10 +22,10 @@ endpackage
|
||||||
module t (/*AUTOARG*/);
|
module t (/*AUTOARG*/);
|
||||||
|
|
||||||
enum integer {
|
enum integer {
|
||||||
EI_A,
|
EI_A,
|
||||||
EI_B,
|
EI_B,
|
||||||
EI_C
|
EI_C
|
||||||
} m_state;
|
} m_state;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
m_state = EI_A;
|
m_state = EI_A;
|
||||||
|
|
|
||||||
|
|
@ -14,12 +14,12 @@ module t (/*AUTOARG*/
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
typedef enum [3:0] {
|
typedef enum [3:0] {
|
||||||
E01 = 1,
|
E01 = 1,
|
||||||
E03 = 3,
|
E03 = 3,
|
||||||
E04 = 4
|
E04 = 4
|
||||||
} my_t;
|
} my_t;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
my_t e;
|
my_t e;
|
||||||
|
|
||||||
int arrayfits [e.num]; // Check can use as constant
|
int arrayfits [e.num]; // Check can use as constant
|
||||||
|
|
@ -49,7 +49,7 @@ module t (/*AUTOARG*/
|
||||||
//
|
//
|
||||||
all = "";
|
all = "";
|
||||||
for (my_t e = e.first; e != e.last; e = e.next) begin
|
for (my_t e = e.first; e != e.last; e = e.next) begin
|
||||||
all = {all, e.name};
|
all = {all, e.name};
|
||||||
end
|
end
|
||||||
e = e.last;
|
e = e.last;
|
||||||
all = {all, e.name};
|
all = {all, e.name};
|
||||||
|
|
@ -60,42 +60,42 @@ module t (/*AUTOARG*/
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
e <= E01;
|
e <= E01;
|
||||||
end
|
end
|
||||||
else if (cyc==1) begin
|
else if (cyc==1) begin
|
||||||
`checks(e.name, "E01");
|
`checks(e.name, "E01");
|
||||||
`checkh(e.next, E03);
|
`checkh(e.next, E03);
|
||||||
`checkh(e.next(1), E03);
|
`checkh(e.next(1), E03);
|
||||||
`checkh(e.next(2), E04);
|
`checkh(e.next(2), E04);
|
||||||
`checkh(e.prev, E04);
|
`checkh(e.prev, E04);
|
||||||
`checkh(e.prev(1), E04);
|
`checkh(e.prev(1), E04);
|
||||||
`checkh(e.prev(2), E03);
|
`checkh(e.prev(2), E03);
|
||||||
e <= E03;
|
e <= E03;
|
||||||
end
|
end
|
||||||
else if (cyc==2) begin
|
else if (cyc==2) begin
|
||||||
`checks(e.name, "E03");
|
`checks(e.name, "E03");
|
||||||
`checkh(e.next, E04);
|
`checkh(e.next, E04);
|
||||||
`checkh(e.next(1), E04);
|
`checkh(e.next(1), E04);
|
||||||
`checkh(e.next(2), E01);
|
`checkh(e.next(2), E01);
|
||||||
`checkh(e.prev, E01);
|
`checkh(e.prev, E01);
|
||||||
`checkh(e.prev(1), E01);
|
`checkh(e.prev(1), E01);
|
||||||
`checkh(e.prev(2), E04);
|
`checkh(e.prev(2), E04);
|
||||||
e <= E04;
|
e <= E04;
|
||||||
end
|
end
|
||||||
else if (cyc==3) begin
|
else if (cyc==3) begin
|
||||||
`checks(e.name, "E04");
|
`checks(e.name, "E04");
|
||||||
`checkh(e.next, E01);
|
`checkh(e.next, E01);
|
||||||
`checkh(e.next(1), E01);
|
`checkh(e.next(1), E01);
|
||||||
`checkh(e.next(2), E03);
|
`checkh(e.next(2), E03);
|
||||||
`checkh(e.prev, E03);
|
`checkh(e.prev, E03);
|
||||||
`checkh(e.prev(1), E03);
|
`checkh(e.prev(1), E03);
|
||||||
`checkh(e.prev(2), E01);
|
`checkh(e.prev(2), E01);
|
||||||
e <= E01;
|
e <= E01;
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -56,8 +56,8 @@ module t (/*AUTOARG*/
|
||||||
reg c;
|
reg c;
|
||||||
|
|
||||||
test test_i (/*AUTOINST*/
|
test test_i (/*AUTOINST*/
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk));
|
.clk (clk));
|
||||||
|
|
||||||
// This is a compile time only test. Immediately finish
|
// This is a compile time only test. Immediately finish
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
|
|
@ -76,7 +76,7 @@ module test (/*AUTOARG*/
|
||||||
|
|
||||||
// Use the enumeration size to initialize a dynamic array
|
// Use the enumeration size to initialize a dynamic array
|
||||||
t_pinid e;
|
t_pinid e;
|
||||||
int myarray1 [] = new [e.num];
|
int myarray1 [] = new [e.num];
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
|
|
||||||
|
|
@ -87,18 +87,18 @@ module test (/*AUTOARG*/
|
||||||
e = e.first;
|
e = e.first;
|
||||||
|
|
||||||
forever begin
|
forever begin
|
||||||
myarray1[e] <= e.prev;
|
myarray1[e] <= e.prev;
|
||||||
|
|
||||||
`ifdef TEST_VERBOSE
|
`ifdef TEST_VERBOSE
|
||||||
$write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]);
|
$write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]);
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
if (e == e.last) begin
|
if (e == e.last) begin
|
||||||
break;
|
break;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
e = e.next;
|
e = e.next;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,7 @@ module t (/*AUTOARG*/
|
||||||
input clk;
|
input clk;
|
||||||
// No verilator_public needed, because it's outside the "" in the $c statement
|
// No verilator_public needed, because it's outside the "" in the $c statement
|
||||||
reg [7:0] cyc; initial cyc = 0;
|
reg [7:0] cyc; initial cyc = 0;
|
||||||
reg c_worked;
|
reg c_worked;
|
||||||
reg [8:0] c_wider;
|
reg [8:0] c_wider;
|
||||||
|
|
||||||
wire one = 1'b1;
|
wire one = 1'b1;
|
||||||
|
|
@ -28,23 +28,23 @@ module t (/*AUTOARG*/
|
||||||
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
|
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
|
||||||
|
|
||||||
if (cyc == 8'd1) begin
|
if (cyc == 8'd1) begin
|
||||||
c_worked <= 0;
|
c_worked <= 0;
|
||||||
end
|
end
|
||||||
if (cyc == 8'd2) begin
|
if (cyc == 8'd2) begin
|
||||||
`ifdef VERILATOR
|
`ifdef VERILATOR
|
||||||
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
|
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
|
||||||
$c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");");
|
$c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");");
|
||||||
c_worked <= $c("this->my_function()");
|
c_worked <= $c("this->my_function()");
|
||||||
c_wider <= $c9("0x10");
|
c_wider <= $c9("0x10");
|
||||||
`else
|
`else
|
||||||
c_worked <= 1'b1;
|
c_worked <= 1'b1;
|
||||||
c_wider <= 9'h10;
|
c_wider <= 9'h10;
|
||||||
`endif
|
`endif
|
||||||
end
|
end
|
||||||
if (cyc == 8'd3) begin
|
if (cyc == 8'd3) begin
|
||||||
if (c_worked !== 1'b1) $stop;
|
if (c_worked !== 1'b1) $stop;
|
||||||
if (c_wider !== 9'h10) $stop;
|
if (c_wider !== 9'h10) $stop;
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -19,14 +19,14 @@ module t (/*AUTOARG*/
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
cyc <= cyc + 8'd1;
|
cyc <= cyc + 8'd1;
|
||||||
if (cyc == 8'd1) begin
|
if (cyc == 8'd1) begin
|
||||||
in <= 32'h10;
|
in <= 32'h10;
|
||||||
end
|
end
|
||||||
if (cyc == 8'd2) begin
|
if (cyc == 8'd2) begin
|
||||||
if (out != 32'h11) $stop;
|
if (out != 32'h11) $stop;
|
||||||
end
|
end
|
||||||
if (cyc == 8'd9) begin
|
if (cyc == 8'd9) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
@ -47,13 +47,13 @@ module t_extend_class_v (/*AUTOARG*/
|
||||||
end
|
end
|
||||||
|
|
||||||
`systemc_header
|
`systemc_header
|
||||||
#include "t_extend_class_c.h" // Header for contained object
|
#include "t_extend_class_c.h" // Header for contained object
|
||||||
`systemc_interface
|
`systemc_interface
|
||||||
t_extend_class_c* m_myobjp; // Pointer to object we are embedding
|
t_extend_class_c* m_myobjp; // Pointer to object we are embedding
|
||||||
`systemc_ctor
|
`systemc_ctor
|
||||||
m_myobjp = new t_extend_class_c(); // Construct contained object
|
m_myobjp = new t_extend_class_c(); // Construct contained object
|
||||||
`systemc_dtor
|
`systemc_dtor
|
||||||
delete m_myobjp; // Destruct contained object
|
delete m_myobjp; // Destruct contained object
|
||||||
`verilog
|
`verilog
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -10,25 +10,25 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
|
|
||||||
reg [89:0] in;
|
reg [89:0] in;
|
||||||
|
|
||||||
/*AUTOWIRE*/
|
/*AUTOWIRE*/
|
||||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||||
wire [89:0] out; // From test of Test.v
|
wire [89:0] out; // From test of Test.v
|
||||||
wire [44:0] line0;
|
wire [44:0] line0;
|
||||||
wire [44:0] line1;
|
wire [44:0] line1;
|
||||||
// End of automatics
|
// End of automatics
|
||||||
|
|
||||||
Test test (/*AUTOINST*/
|
Test test (/*AUTOINST*/
|
||||||
// Outputs
|
// Outputs
|
||||||
.out (out[89:0]),
|
.out (out[89:0]),
|
||||||
.line0 (line0[44:0]),
|
.line0 (line0[44:0]),
|
||||||
.line1 (line1[44:0]),
|
.line1 (line1[44:0]),
|
||||||
// Inputs
|
// Inputs
|
||||||
.clk (clk),
|
.clk (clk),
|
||||||
.in (in[89:0]));
|
.in (in[89:0]));
|
||||||
|
|
||||||
// Test loop
|
// Test loop
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
|
|
@ -37,18 +37,18 @@ module t (/*AUTOARG*/
|
||||||
`endif
|
`endif
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
|
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
|
||||||
end
|
end
|
||||||
else if (cyc==10) begin
|
else if (cyc==10) begin
|
||||||
if (in==out) begin
|
if (in==out) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
$write("*-* Failed!! *-*\n");
|
$write("*-* Failed!! *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -64,9 +64,9 @@ module Test (/*AUTOARG*/
|
||||||
input clk;
|
input clk;
|
||||||
input [89:0] in;
|
input [89:0] in;
|
||||||
|
|
||||||
output reg [44:0] line0;
|
output reg [44:0] line0;
|
||||||
output reg [44:0] line1;
|
output reg [44:0] line1;
|
||||||
output reg [89:0] out;
|
output reg [89:0] out;
|
||||||
|
|
||||||
assign {line0,line1} = in;
|
assign {line0,line1} = in;
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
|
|
|
||||||
|
|
@ -23,8 +23,8 @@ endmodule
|
||||||
module l3 (input tmp);
|
module l3 (input tmp);
|
||||||
initial begin
|
initial begin
|
||||||
if (tmp) begin
|
if (tmp) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -10,9 +10,9 @@ module t (/*AUTOARG*/
|
||||||
);
|
);
|
||||||
input clk;
|
input clk;
|
||||||
|
|
||||||
integer cyc = 0;
|
integer cyc = 0;
|
||||||
reg [63:0] crc;
|
reg [63:0] crc;
|
||||||
reg [63:0] sum;
|
reg [63:0] sum;
|
||||||
|
|
||||||
// Take CRC data and apply to testblock inputs
|
// Take CRC data and apply to testblock inputs
|
||||||
wire [3:0] l_stop = crc[3:0];
|
wire [3:0] l_stop = crc[3:0];
|
||||||
|
|
@ -38,26 +38,26 @@ module t (/*AUTOARG*/
|
||||||
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
|
||||||
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
|
||||||
if (cyc==0) begin
|
if (cyc==0) begin
|
||||||
// Setup
|
// Setup
|
||||||
crc <= 64'h5aef0c8d_d70a4497;
|
crc <= 64'h5aef0c8d_d70a4497;
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<10) begin
|
else if (cyc<10) begin
|
||||||
sum <= 64'h0;
|
sum <= 64'h0;
|
||||||
end
|
end
|
||||||
else if (cyc<90) begin
|
else if (cyc<90) begin
|
||||||
if (out0!==out1) $stop;
|
if (out0!==out1) $stop;
|
||||||
if (out0!==out2) $stop;
|
if (out0!==out2) $stop;
|
||||||
if (out0!==out3) $stop;
|
if (out0!==out3) $stop;
|
||||||
end
|
end
|
||||||
else if (cyc==99) begin
|
else if (cyc==99) begin
|
||||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
|
||||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||||
// What checksum will we end up with (above print should match)
|
// What checksum will we end up with (above print should match)
|
||||||
`define EXPECTED_SUM 64'h293e9f9798e97da0
|
`define EXPECTED_SUM 64'h293e9f9798e97da0
|
||||||
if (sum !== `EXPECTED_SUM) $stop;
|
if (sum !== `EXPECTED_SUM) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -65,25 +65,25 @@ module t (/*AUTOARG*/
|
||||||
input [3:0] loop_stop;
|
input [3:0] loop_stop;
|
||||||
input [3:0] loop_break;
|
input [3:0] loop_break;
|
||||||
input [3:0] loop_continue;
|
input [3:0] loop_continue;
|
||||||
integer i;
|
integer i;
|
||||||
reg broken;
|
reg broken;
|
||||||
|
|
||||||
Test0 = 0;
|
Test0 = 0;
|
||||||
broken = 0;
|
broken = 0;
|
||||||
begin
|
begin
|
||||||
for (i=1; i<20; i=i+1) begin
|
for (i=1; i<20; i=i+1) begin
|
||||||
if (!broken) begin
|
if (!broken) begin
|
||||||
Test0 = Test0 + 1;
|
Test0 = Test0 + 1;
|
||||||
if (i[3:0] != loop_continue) begin // continue
|
if (i[3:0] != loop_continue) begin // continue
|
||||||
if (i[3:0] == loop_break) begin
|
if (i[3:0] == loop_break) begin
|
||||||
broken = 1'b1;
|
broken = 1'b1;
|
||||||
end
|
end
|
||||||
if (!broken) begin
|
if (!broken) begin
|
||||||
Test0 = Test0 + i[15:0];
|
Test0 = Test0 + i[15:0];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endfunction
|
endfunction
|
||||||
|
|
||||||
|
|
@ -91,17 +91,17 @@ module t (/*AUTOARG*/
|
||||||
input [3:0] loop_stop;
|
input [3:0] loop_stop;
|
||||||
input [3:0] loop_break;
|
input [3:0] loop_break;
|
||||||
input [3:0] loop_continue;
|
input [3:0] loop_continue;
|
||||||
integer i;
|
integer i;
|
||||||
|
|
||||||
Test1 = 0;
|
Test1 = 0;
|
||||||
begin : outer_block
|
begin : outer_block
|
||||||
for (i=1; i<20; i=i+1) begin : inner_block
|
for (i=1; i<20; i=i+1) begin : inner_block
|
||||||
Test1 = Test1 + 1;
|
Test1 = Test1 + 1;
|
||||||
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
|
// continue, IE jump to end-of-inner_block. Must be inside inner_block.
|
||||||
if (i[3:0] == loop_continue) disable inner_block;
|
if (i[3:0] == loop_continue) disable inner_block;
|
||||||
// break, IE jump to end-of-outer_block. Must be inside outer_block.
|
// break, IE jump to end-of-outer_block. Must be inside outer_block.
|
||||||
if (i[3:0] == loop_break) disable outer_block;
|
if (i[3:0] == loop_break) disable outer_block;
|
||||||
Test1 = Test1 + i[15:0];
|
Test1 = Test1 + i[15:0];
|
||||||
end : inner_block
|
end : inner_block
|
||||||
end : outer_block
|
end : outer_block
|
||||||
endfunction
|
endfunction
|
||||||
|
|
@ -110,15 +110,15 @@ module t (/*AUTOARG*/
|
||||||
input [3:0] loop_stop;
|
input [3:0] loop_stop;
|
||||||
input [3:0] loop_break;
|
input [3:0] loop_break;
|
||||||
input [3:0] loop_continue;
|
input [3:0] loop_continue;
|
||||||
integer i;
|
integer i;
|
||||||
|
|
||||||
Test2 = 0;
|
Test2 = 0;
|
||||||
begin
|
begin
|
||||||
for (i=1; i<20; i=i+1) begin
|
for (i=1; i<20; i=i+1) begin
|
||||||
Test2 = Test2 + 1;
|
Test2 = Test2 + 1;
|
||||||
if (i[3:0] == loop_continue) continue;
|
if (i[3:0] == loop_continue) continue;
|
||||||
if (i[3:0] == loop_break) break;
|
if (i[3:0] == loop_break) break;
|
||||||
Test2 = Test2 + i[15:0];
|
Test2 = Test2 + i[15:0];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endfunction
|
endfunction
|
||||||
|
|
@ -127,16 +127,16 @@ module t (/*AUTOARG*/
|
||||||
input [3:0] loop_stop;
|
input [3:0] loop_stop;
|
||||||
input [3:0] loop_break;
|
input [3:0] loop_break;
|
||||||
input [3:0] loop_continue;
|
input [3:0] loop_continue;
|
||||||
integer i;
|
integer i;
|
||||||
|
|
||||||
Test3 = 0;
|
Test3 = 0;
|
||||||
begin
|
begin
|
||||||
for (i=1; i<20; i=i+1) begin
|
for (i=1; i<20; i=i+1) begin
|
||||||
Test3 = Test3 + 1;
|
Test3 = Test3 + 1;
|
||||||
if (i[3:0] == loop_continue) continue;
|
if (i[3:0] == loop_continue) continue;
|
||||||
// return, IE jump to end-of-function optionally setting return value
|
// return, IE jump to end-of-function optionally setting return value
|
||||||
if (i[3:0] == loop_break) return Test3;
|
if (i[3:0] == loop_break) return Test3;
|
||||||
Test3 = Test3 + i[15:0];
|
Test3 = Test3 + i[15:0];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endfunction
|
endfunction
|
||||||
|
|
|
||||||
|
|
@ -19,7 +19,7 @@ module t (/*AUTOARG*/
|
||||||
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
||||||
hit_count = 0;
|
hit_count = 0;
|
||||||
for (j=0; j < 64; j=j+1) begin
|
for (j=0; j < 64; j=j+1) begin
|
||||||
hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]};
|
hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]};
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -27,7 +27,7 @@ module t (/*AUTOARG*/
|
||||||
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
||||||
hit_count2 = 0;
|
hit_count2 = 0;
|
||||||
for (j=63; j >= 0; j=j-1) begin
|
for (j=63; j >= 0; j=j-1) begin
|
||||||
hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]};
|
hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]};
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -35,7 +35,7 @@ module t (/*AUTOARG*/
|
||||||
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
||||||
hit_count3 = 0;
|
hit_count3 = 0;
|
||||||
for (j=63; j > 0; j=j-1) begin
|
for (j=63; j > 0; j=j-1) begin
|
||||||
if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1;
|
if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -44,9 +44,9 @@ module t (/*AUTOARG*/
|
||||||
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
|
||||||
wide_for_count = 0;
|
wide_for_count = 0;
|
||||||
for (wide_for_index = 128'hff_00000000_00000000;
|
for (wide_for_index = 128'hff_00000000_00000000;
|
||||||
wide_for_index < 128'hff_00000000_00000100;
|
wide_for_index < 128'hff_00000000_00000100;
|
||||||
wide_for_index = wide_for_index + 2) begin
|
wide_for_index = wide_for_index + 2) begin
|
||||||
wide_for_count = wide_for_count+32'h1;
|
wide_for_count = wide_for_count+32'h1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -74,26 +74,26 @@ module t (/*AUTOARG*/
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
cam_lookup_hit_vector <= 0;
|
cam_lookup_hit_vector <= 0;
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
cam_lookup_hit_vector <= 64'h00010000_00010000;
|
cam_lookup_hit_vector <= 64'h00010000_00010000;
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
if (hit_count != 32'd2) $stop;
|
if (hit_count != 32'd2) $stop;
|
||||||
if (hit_count2 != 32'd2) $stop;
|
if (hit_count2 != 32'd2) $stop;
|
||||||
if (hit_count3 != 32'd2) $stop;
|
if (hit_count3 != 32'd2) $stop;
|
||||||
cam_lookup_hit_vector <= 64'h01010010_00010001;
|
cam_lookup_hit_vector <= 64'h01010010_00010001;
|
||||||
end
|
end
|
||||||
if (cyc==3) begin
|
if (cyc==3) begin
|
||||||
if (hit_count != 32'd5) $stop;
|
if (hit_count != 32'd5) $stop;
|
||||||
if (hit_count2 != 32'd5) $stop;
|
if (hit_count2 != 32'd5) $stop;
|
||||||
if (hit_count3 != 32'd4) $stop;
|
if (hit_count3 != 32'd4) $stop;
|
||||||
if (wide_for_count != 32'h80) $stop;
|
if (wide_for_count != 32'h80) $stop;
|
||||||
end
|
end
|
||||||
if (cyc==9) begin
|
if (cyc==9) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -20,14 +20,14 @@ module t (/*AUTOARG*/
|
||||||
task show;
|
task show;
|
||||||
input [8*8-1:0] str;
|
input [8*8-1:0] str;
|
||||||
reg [7:0] char;
|
reg [7:0] char;
|
||||||
integer loc;
|
integer loc;
|
||||||
begin
|
begin
|
||||||
$write("[%0t] ", $time);
|
$write("[%0t] ", $time);
|
||||||
strings.stringStart(8*8-1);
|
strings.stringStart(8*8-1);
|
||||||
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
|
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
|
||||||
$write("%c",char);
|
$write("%c",char);
|
||||||
end
|
end
|
||||||
$write("\n");
|
$write("\n");
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
|
|
@ -35,17 +35,17 @@ module t (/*AUTOARG*/
|
||||||
integer cyc; initial cyc=1;
|
integer cyc; initial cyc=1;
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
if (cyc!=0) begin
|
if (cyc!=0) begin
|
||||||
cyc <= cyc + 1;
|
cyc <= cyc + 1;
|
||||||
if (cyc==1) begin
|
if (cyc==1) begin
|
||||||
show("hello\000xx");
|
show("hello\000xx");
|
||||||
end
|
end
|
||||||
if (cyc==2) begin
|
if (cyc==2) begin
|
||||||
show("world\000xx");
|
show("world\000xx");
|
||||||
end
|
end
|
||||||
if (cyc==4) begin
|
if (cyc==4) begin
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -57,7 +57,7 @@ module strings;
|
||||||
task stringStart;
|
task stringStart;
|
||||||
input [31:0] bits;
|
input [31:0] bits;
|
||||||
begin
|
begin
|
||||||
index = (bits-1)/8;
|
index = (bits-1)/8;
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
|
|
@ -69,9 +69,9 @@ module strings;
|
||||||
function [7:0] stringByte;
|
function [7:0] stringByte;
|
||||||
input [8*8-1:0] str;
|
input [8*8-1:0] str;
|
||||||
begin
|
begin
|
||||||
if (index<=0) stringByte=8'h0;
|
if (index<=0) stringByte=8'h0;
|
||||||
else stringByte = str[index*8 +: 8];
|
else stringByte = str[index*8 +: 8];
|
||||||
index = index - 1;
|
index = index - 1;
|
||||||
end
|
end
|
||||||
endfunction
|
endfunction
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -22,10 +22,10 @@ module t (/*AUTOARG*/
|
||||||
|
|
||||||
always @* begin
|
always @* begin
|
||||||
for (i=ARW-1;i>0;i=i-1) begin
|
for (i=ARW-1;i>0;i=i-1) begin
|
||||||
priority_mask[i]=1'b0;
|
priority_mask[i]=1'b0;
|
||||||
// vvvv=== note j=j not j=i; was bug
|
// vvvv=== note j=j not j=i; was bug
|
||||||
for( j=j;j>=0;j=j-1)
|
for( j=j;j>=0;j=j-1)
|
||||||
priority_mask[i]=priority_mask[j] | muxed_requests[j];
|
priority_mask[i]=priority_mask[j] | muxed_requests[j];
|
||||||
end
|
end
|
||||||
//Bit zero is always enabled
|
//Bit zero is always enabled
|
||||||
priority_mask[0]=1'b0;
|
priority_mask[0]=1'b0;
|
||||||
|
|
|
||||||
|
|
@ -18,36 +18,36 @@ module t (/*AUTOARG*/
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
cyc <= cyc+8'd1;
|
cyc <= cyc+8'd1;
|
||||||
if (cyc == 8'd1) begin
|
if (cyc == 8'd1) begin
|
||||||
$write("[%0t] t_loop: Running\n", $time);
|
$write("[%0t] t_loop: Running\n", $time);
|
||||||
// Unwind <
|
// Unwind <
|
||||||
loops = 0;
|
loops = 0;
|
||||||
loops2 = 0;
|
loops2 = 0;
|
||||||
for (int i=0; i<16; i=i+1) begin
|
for (int i=0; i<16; i=i+1) begin
|
||||||
loops = loops + i; // surefire lint_off_line ASWEMB
|
loops = loops + i; // surefire lint_off_line ASWEMB
|
||||||
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
|
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
|
||||||
end
|
end
|
||||||
if (loops !== 120) $stop;
|
if (loops !== 120) $stop;
|
||||||
if (loops2 !== 120) $stop;
|
if (loops2 !== 120) $stop;
|
||||||
// Check we can declare the same signal twice
|
// Check we can declare the same signal twice
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (int i=0; i<=16; i=i+1) begin
|
for (int i=0; i<=16; i=i+1) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (loops !== 17) $stop;
|
if (loops !== 17) $stop;
|
||||||
// Check type is correct
|
// Check type is correct
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (byte unsigned i=5; i>4; i=i+1) begin
|
for (byte unsigned i=5; i>4; i=i+1) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (loops !== 251) $stop;
|
if (loops !== 251) $stop;
|
||||||
// Check large loops
|
// Check large loops
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (int i=0; i<100000; i=i+1) begin
|
for (int i=0; i<100000; i=i+1) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (loops !== 100000) $stop;
|
if (loops !== 100000) $stop;
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -19,98 +19,98 @@ module t (/*AUTOARG*/
|
||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
cyc <= cyc+8'd1;
|
cyc <= cyc+8'd1;
|
||||||
if (cyc == 8'd1) begin
|
if (cyc == 8'd1) begin
|
||||||
$write("[%0t] t_loop: Running\n", $time);
|
$write("[%0t] t_loop: Running\n", $time);
|
||||||
// Unwind <
|
// Unwind <
|
||||||
loops = 0;
|
loops = 0;
|
||||||
loops2 = 0;
|
loops2 = 0;
|
||||||
for (i=0; i<16; i=i+1) begin
|
for (i=0; i<16; i=i+1) begin
|
||||||
loops = loops + i; // surefire lint_off_line ASWEMB
|
loops = loops + i; // surefire lint_off_line ASWEMB
|
||||||
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
|
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
|
||||||
end
|
end
|
||||||
if (i !== 16) $stop;
|
if (i !== 16) $stop;
|
||||||
if (loops !== 120) $stop;
|
if (loops !== 120) $stop;
|
||||||
if (loops2 !== 120) $stop;
|
if (loops2 !== 120) $stop;
|
||||||
// Unwind <=
|
// Unwind <=
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=0; i<=16; i=i+1) begin
|
for (i=0; i<=16; i=i+1) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (i !== 17) $stop;
|
if (i !== 17) $stop;
|
||||||
if (loops !== 17) $stop;
|
if (loops !== 17) $stop;
|
||||||
// Don't unwind breaked loops
|
// Don't unwind breaked loops
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=0; i<16; i=i+1) begin
|
for (i=0; i<16; i=i+1) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
if (i==7) i=99; // break out of loop
|
if (i==7) i=99; // break out of loop
|
||||||
end
|
end
|
||||||
if (loops !== 8) $stop;
|
if (loops !== 8) $stop;
|
||||||
// Don't unwind large loops!
|
// Don't unwind large loops!
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=0; i<100000; i=i+1) begin
|
for (i=0; i<100000; i=i+1) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (loops !== 100000) $stop;
|
if (loops !== 100000) $stop;
|
||||||
// Test post-increment
|
// Test post-increment
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=0; i<=16; i++) begin
|
for (i=0; i<=16; i++) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (i !== 17) $stop;
|
if (i !== 17) $stop;
|
||||||
if (loops !== 17) $stop;
|
if (loops !== 17) $stop;
|
||||||
// Test pre-increment
|
// Test pre-increment
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=0; i<=16; ++i) begin
|
for (i=0; i<=16; ++i) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (i !== 17) $stop;
|
if (i !== 17) $stop;
|
||||||
if (loops !== 17) $stop;
|
if (loops !== 17) $stop;
|
||||||
// Test post-decrement
|
// Test post-decrement
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=16; i>=0; i--) begin
|
for (i=16; i>=0; i--) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (i !== -1) $stop;
|
if (i !== -1) $stop;
|
||||||
if (loops !== 17) $stop;
|
if (loops !== 17) $stop;
|
||||||
// Test pre-decrement
|
// Test pre-decrement
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=16; i>=0; --i) begin
|
for (i=16; i>=0; --i) begin
|
||||||
loops = loops + 1;
|
loops = loops + 1;
|
||||||
end
|
end
|
||||||
if (i !== -1) $stop;
|
if (i !== -1) $stop;
|
||||||
if (loops !== 17) $stop;
|
if (loops !== 17) $stop;
|
||||||
//
|
//
|
||||||
// 1800-2017 optionals init/expr/incr
|
// 1800-2017 optionals init/expr/incr
|
||||||
loops = 0;
|
loops = 0;
|
||||||
i = 0;
|
i = 0;
|
||||||
for (; i<10; ++i) ++loops;
|
for (; i<10; ++i) ++loops;
|
||||||
if (loops !== 10) $stop;
|
if (loops !== 10) $stop;
|
||||||
//
|
//
|
||||||
loops = 0;
|
loops = 0;
|
||||||
i = 0;
|
i = 0;
|
||||||
for (i=0; i<10; ) begin ++loops; ++i; end
|
for (i=0; i<10; ) begin ++loops; ++i; end
|
||||||
if (loops !== 10) $stop;
|
if (loops !== 10) $stop;
|
||||||
//
|
//
|
||||||
loops = 0;
|
loops = 0;
|
||||||
i = 0;
|
i = 0;
|
||||||
for (; ; ++i) begin ++loops; break; end
|
for (; ; ++i) begin ++loops; break; end
|
||||||
if (loops !== 1) $stop;
|
if (loops !== 1) $stop;
|
||||||
//
|
//
|
||||||
// bug1605
|
// bug1605
|
||||||
i = 1;
|
i = 1;
|
||||||
for (i=20; 0; ) ;
|
for (i=20; 0; ) ;
|
||||||
if (i != 20) $stop;
|
if (i != 20) $stop;
|
||||||
for (i=30; i<10; i++) ;
|
for (i=30; i<10; i++) ;
|
||||||
if (i != 30) $stop;
|
if (i != 30) $stop;
|
||||||
// Comma
|
// Comma
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=0; i<20; ++i, ++loops);
|
for (i=0; i<20; ++i, ++loops);
|
||||||
if (loops !== 20) $stop;
|
if (loops !== 20) $stop;
|
||||||
loops = 0;
|
loops = 0;
|
||||||
for (i=0; i<20; ++loops, ++i);
|
for (i=0; i<20; ++loops, ++i);
|
||||||
if (loops !== 20) $stop;
|
if (loops !== 20) $stop;
|
||||||
//
|
//
|
||||||
$write("*-* All Finished *-*\n");
|
$write("*-* All Finished *-*\n");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -68,12 +68,12 @@ module t;
|
||||||
function [2:0] add;
|
function [2:0] add;
|
||||||
input [2:0] fromv;
|
input [2:0] fromv;
|
||||||
begin
|
begin
|
||||||
add = fromv + 3'd1;
|
add = fromv + 3'd1;
|
||||||
begin : named
|
begin : named
|
||||||
reg [31:0] flocal;
|
reg [31:0] flocal;
|
||||||
flocal = 1;
|
flocal = 1;
|
||||||
rglobal = rglobal + flocal;
|
rglobal = rglobal + flocal;
|
||||||
end : named // SystemVerilog end labels
|
end : named // SystemVerilog end labels
|
||||||
end
|
end
|
||||||
endfunction
|
endfunction
|
||||||
|
|
||||||
|
|
@ -81,26 +81,26 @@ module t;
|
||||||
input [3:0] fromv; // Different fromv than the 'fromv' signal above
|
input [3:0] fromv; // Different fromv than the 'fromv' signal above
|
||||||
reg one;
|
reg one;
|
||||||
begin : named
|
begin : named
|
||||||
reg [1:0] flocal;
|
reg [1:0] flocal;
|
||||||
// Function calling a function
|
// Function calling a function
|
||||||
one = 1'b1;
|
one = 1'b1;
|
||||||
munge4 = {one, add(fromv[2:0])};
|
munge4 = {one, add(fromv[2:0])};
|
||||||
end
|
end
|
||||||
endfunction
|
endfunction
|
||||||
|
|
||||||
task setit;
|
task setit;
|
||||||
reg [31:0] temp;
|
reg [31:0] temp;
|
||||||
begin
|
begin
|
||||||
temp = rglobal + 32'h1;
|
temp = rglobal + 32'h1;
|
||||||
rglobal = temp + 32'h1;
|
rglobal = temp + 32'h1;
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
task incr (
|
task incr (
|
||||||
// Check a V2K style input/output list
|
// Check a V2K style input/output list
|
||||||
output [31:0] z,
|
output [31:0] z,
|
||||||
input [31:0] a, inc
|
input [31:0] a, inc
|
||||||
);
|
);
|
||||||
z = a + inc;
|
z = a + inc;
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
|
|
@ -118,8 +118,8 @@ module t;
|
||||||
input [3:0] bitnum;
|
input [3:0] bitnum;
|
||||||
reg [4:0] bitnum2;
|
reg [4:0] bitnum2;
|
||||||
begin
|
begin
|
||||||
bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation
|
bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation
|
||||||
vector[bitnum2] = vector[bitnum2] ^ 1'b1;
|
vector[bitnum2] = vector[bitnum2] ^ 1'b1;
|
||||||
end
|
end
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
|
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue