additional testcases for function and coverage, including nested interfaces, passing multidimensional arrays through module hierarchy, and dotted reference of inner interfaces.
This commit is contained in:
Eric Mejdrich
parent
61673258a3
commit
2a7daea2c3
105
src/V3Inst.cpp
105
src/V3Inst.cpp
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@ -446,6 +446,111 @@ private:
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}
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} else {
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AstVar* const pinVarp = nodep->modVarp();
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// Multi-dim whole-array iface pin fanout: cartesian-product the port's
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// nested UnpackArrayDType layers and emit one pin + per-element var per cell.
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// For 1-dim falls through to the original code below.
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std::vector<const AstUnpackArrayDType*> portArrs;
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for (AstNodeDType* d = pinVarp->dtypep()->skipRefp(); d;) {
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if (const AstUnpackArrayDType* const arrp = VN_CAST(d, UnpackArrayDType)) {
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portArrs.push_back(arrp);
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d = arrp->subDTypep()->skipRefp();
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} else {
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break;
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}
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}
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if (portArrs.size() >= 2) {
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AstIfaceRefDType* const portIrp
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= VN_CAST(portArrs.back()->subDTypep()->skipRefp(), IfaceRefDType);
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if (!portIrp || portIrp->isVirtual()) return;
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const int ndim = static_cast<int>(portArrs.size());
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std::vector<int> sizes(ndim);
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int totalElems = 1;
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for (int d = 0; d < ndim; ++d) {
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sizes[d] = portArrs[d]->elementsConst();
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totalElems *= sizes[d];
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}
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const AstVarRef* const varrefp = VN_CAST(nodep->exprp(), VarRef);
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if (!varrefp) {
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nodep->exprp()->v3error("Unexpected connection to multi-dim arrayed port");
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return;
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}
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std::vector<const AstUnpackArrayDType*> exprArrs;
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for (AstNodeDType* d = varrefp->dtypep()->skipRefp(); d;) {
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if (const AstUnpackArrayDType* const arrp = VN_CAST(d, UnpackArrayDType)) {
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exprArrs.push_back(arrp);
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d = arrp->subDTypep()->skipRefp();
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} else {
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break;
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}
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}
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if (exprArrs.size() != static_cast<size_t>(ndim)) {
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nodep->exprp()->v3error(
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"Multi-dim iface pin expression rank does not match port");
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return;
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}
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AstNode* prevp = nullptr;
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AstNode* prevPinp = nullptr;
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std::vector<int> idx(ndim, 0);
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for (int n = 0; n < totalElems; ++n) {
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int rem = n;
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for (int d = ndim - 1; d >= 0; --d) {
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idx[d] = rem % sizes[d];
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rem /= sizes[d];
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}
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string portSuffix;
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string exprSuffix;
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for (int d = 0; d < ndim; ++d) {
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portSuffix += "__BRA__"
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+ AstNode::encodeNumber(portArrs[d]->lo() + idx[d])
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+ "__KET__";
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exprSuffix += "__BRA__"
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+ AstNode::encodeNumber(exprArrs[d]->lo() + idx[d])
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+ "__KET__";
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}
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const string varNewName = pinVarp->name() + portSuffix;
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AstVar* varNewp = nullptr;
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if (!pinVarp->backp()) {
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varNewp = m_deModVars.find(varNewName);
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} else {
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portIrp->cellp(nullptr);
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varNewp = pinVarp->cloneTree(false);
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varNewp->name(varNewName);
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varNewp->origName(varNewp->origName() + portSuffix);
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varNewp->dtypep(portIrp);
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m_deModVars.insert(varNewp);
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if (!prevp) {
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prevp = varNewp;
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} else {
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prevp->addNextHere(varNewp);
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}
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}
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if (!varNewp) {
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if (debug() >= 9) m_deModVars.dump(); // LCOV_EXCL_LINE
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nodep->v3fatalSrc("Module dearray failed for "
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<< AstNode::prettyNameQ(varNewName));
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}
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AstPin* const newp = nodep->cloneTree(false);
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newp->modVarp(varNewp);
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newp->name(newp->name() + portSuffix);
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AstVarXRef* const newVarXRefp = new AstVarXRef{
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nodep->fileline(), varrefp->name() + exprSuffix, "", VAccess::WRITE};
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newVarXRefp->varp(newp->modVarp());
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newp->exprp()->unlinkFrBack()->deleteTree();
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newp->exprp(newVarXRefp);
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if (!prevPinp) {
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prevPinp = newp;
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} else {
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prevPinp->addNextHere(newp);
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}
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}
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if (prevp) {
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pinVarp->replaceWith(prevp);
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pushDeletep(pinVarp);
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}
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nodep->replaceWith(prevPinp);
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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return;
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}
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const AstUnpackArrayDType* const pinArrp
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= VN_CAST(pinVarp->dtypep()->skipRefp(), UnpackArrayDType);
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if (!pinArrp || !VN_IS(pinArrp->subDTypep()->skipRefp(), IfaceRefDType)) return;
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -0,0 +1,59 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// 3D iface-array port passed to a submodule. t_iface_array_multidim_3d
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// covers 3D local declaration; this covers 3D through a port.
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interface simple_if;
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logic [15:0] data;
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endinterface
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module sink (simple_if b [1:0][1:0][2:0]);
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logic [15:0] chk [1:0][1:0][2:0];
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genvar gi, gj, gk;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_a
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for (gj = 0; gj < 2; gj++) begin : g_b
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for (gk = 0; gk < 3; gk++) begin : g_c
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always_comb chk[gi][gj][gk] = b[gi][gj][gk].data;
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end
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end
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end
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endgenerate
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endmodule
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module t;
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simple_if bus [1:0][1:0][2:0] ();
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sink inst (.b(bus));
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genvar gi, gj, gk;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_drive_a
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for (gj = 0; gj < 2; gj++) begin : g_drive_b
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for (gk = 0; gk < 3; gk++) begin : g_drive_c
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initial bus[gi][gj][gk].data = 16'(gi * 6 + gj * 3 + gk + 1);
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end
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end
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end
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endgenerate
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initial begin
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#1;
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j < 2; j++) begin
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for (int k = 0; k < 3; k++) begin
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if (inst.chk[i][j][k] !== 16'(i * 6 + j * 3 + k + 1)) begin
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$write("%%Error: chk[%0d][%0d][%0d]=%0d expected %0d\n",
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i, j, k, inst.chk[i][j][k], i * 6 + j * 3 + k + 1);
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$stop;
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end
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -0,0 +1,58 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Three-level hierarchy passing a multi-dim iface array by port at each
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// boundary. Top reads leaf's chk array via dotted cross-hier reference,
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// which also exercises the multi-dim dotted-access resolver.
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interface simple_if;
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logic [7:0] data;
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endinterface
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module leaf (simple_if b [1:0][2:0]);
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logic [7:0] chk [1:0][2:0];
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_a
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for (gj = 0; gj < 3; gj++) begin : g_b
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always_comb chk[gi][gj] = b[gi][gj].data;
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end
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end
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endgenerate
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endmodule
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module mid (simple_if b [1:0][2:0]);
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leaf leaf_inst (.b(b));
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endmodule
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module t;
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simple_if bus [1:0][2:0] ();
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mid mid_inst (.b(bus));
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_drive_a
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for (gj = 0; gj < 3; gj++) begin : g_drive_b
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initial bus[gi][gj].data = 8'(gi * 3 + gj + 7);
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end
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end
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endgenerate
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initial begin
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#1;
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j < 3; j++) begin
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if (mid_inst.leaf_inst.chk[i][j] !== 8'(i * 3 + j + 7)) begin
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$write("%%Error: leaf.chk[%0d][%0d]=%0d expected %0d\n",
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i, j, mid_inst.leaf_inst.chk[i][j], i * 3 + j + 7);
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$stop;
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -0,0 +1,59 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Multi-dim iface array ports typed with a modport (both source and sink).
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// Mirrors 1D modport-port coverage in t_interface_array_loop for the
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// multi-dim pin-fanout path.
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interface simple_if;
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logic [7:0] data;
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modport source(output data);
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modport sink(input data);
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endinterface
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module src (simple_if.source b [1:0][2:0]);
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_a
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for (gj = 0; gj < 3; gj++) begin : g_b
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initial b[gi][gj].data = 8'(gi * 3 + gj + 20);
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end
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end
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endgenerate
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endmodule
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module snk (simple_if.sink b [1:0][2:0]);
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logic [7:0] chk [1:0][2:0];
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_a
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for (gj = 0; gj < 3; gj++) begin : g_b
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always_comb chk[gi][gj] = b[gi][gj].data;
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end
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end
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endgenerate
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endmodule
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module t;
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simple_if bus [1:0][2:0] ();
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src src_inst (.b(bus));
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snk snk_inst (.b(bus));
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initial begin
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#1;
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j < 3; j++) begin
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if (snk_inst.chk[i][j] !== 8'(i * 3 + j + 20)) begin
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$write("%%Error: chk[%0d][%0d]=%0d expected %0d\n",
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i, j, snk_inst.chk[i][j], i * 3 + j + 20);
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$stop;
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
|
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
|
||||
# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -0,0 +1,69 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// outer_if contains inner_if; an array of outer_if is passed as a port to
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// a submodule which reaches through to inner_if's signal. Exercises
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// hierarchical iface reference across the fanned-out multi-dim port.
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interface inner_if;
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logic [7:0] data;
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endinterface
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interface outer_if;
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inner_if inner();
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logic [7:0] tag;
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endinterface
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module sink (outer_if b [1:0][1:0]);
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logic [7:0] chk_tag [1:0][1:0];
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logic [7:0] chk_inner [1:0][1:0];
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_a
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for (gj = 0; gj < 2; gj++) begin : g_b
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always_comb chk_tag[gi][gj] = b[gi][gj].tag;
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always_comb chk_inner[gi][gj] = b[gi][gj].inner.data;
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end
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end
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endgenerate
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endmodule
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module t;
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outer_if oarr [1:0][1:0] ();
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sink inst (.b(oarr));
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genvar gi, gj;
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generate
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for (gi = 0; gi < 2; gi++) begin : g_drive_a
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for (gj = 0; gj < 2; gj++) begin : g_drive_b
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initial begin
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oarr[gi][gj].tag = 8'(gi * 16 + gj);
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oarr[gi][gj].inner.data = 8'(gi * 2 + gj + 100);
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end
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end
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end
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endgenerate
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initial begin
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#1;
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j < 2; j++) begin
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if (inst.chk_tag[i][j] !== 8'(i * 16 + j)) begin
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$write("%%Error: chk_tag[%0d][%0d]=%0d expected %0d\n",
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i, j, inst.chk_tag[i][j], i * 16 + j);
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$stop;
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end
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if (inst.chk_inner[i][j] !== 8'(i * 2 + j + 100)) begin
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$write("%%Error: chk_inner[%0d][%0d]=%0d expected %0d\n",
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i, j, inst.chk_inner[i][j], i * 2 + j + 100);
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$stop;
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
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#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of either the GNU Lesser General Public License Version 3
|
||||
# or the Perl Artistic License Version 2.0.
|
||||
# SPDX-FileCopyrightText: 2026 Wilson Snyder
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain.
|
||||
// SPDX-FileCopyrightText: 2026 Wilson Snyder
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// Multi-dim iface array passed as a port to a submodule (the point of
|
||||
// multi-dim iface arrays). Exercises the multi-dim pin-fanout branch in
|
||||
// V3Inst::visit(AstPin) and the multi-dim branch in V3Inst::visit(AstVar)
|
||||
// on the sink's port var.
|
||||
|
||||
interface simple_if;
|
||||
logic [7:0] data;
|
||||
endinterface
|
||||
|
||||
module sink (simple_if b [1:0][2:0]);
|
||||
logic [7:0] chk [1:0][2:0];
|
||||
genvar gi, gj;
|
||||
generate
|
||||
for (gi = 0; gi < 2; gi++) begin : g_a
|
||||
for (gj = 0; gj < 3; gj++) begin : g_b
|
||||
always_comb chk[gi][gj] = b[gi][gj].data;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module t;
|
||||
simple_if bus [1:0][2:0] ();
|
||||
sink inst (.b(bus));
|
||||
|
||||
genvar gi, gj;
|
||||
generate
|
||||
for (gi = 0; gi < 2; gi++) begin : g_drive_a
|
||||
for (gj = 0; gj < 3; gj++) begin : g_drive_b
|
||||
initial bus[gi][gj].data = 8'(gi * 3 + gj + 1);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
for (int i = 0; i < 2; i++) begin
|
||||
for (int j = 0; j < 3; j++) begin
|
||||
if (inst.chk[i][j] !== 8'(i * 3 + j + 1)) begin
|
||||
$write("%%Error: inst.chk[%0d][%0d]=%0d expected %0d\n",
|
||||
i, j, inst.chk[i][j], i * 3 + j + 1);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of either the GNU Lesser General Public License Version 3
|
||||
# or the Perl Artistic License Version 2.0.
|
||||
# SPDX-FileCopyrightText: 2026 Wilson Snyder
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain.
|
||||
// SPDX-FileCopyrightText: 2026 Wilson Snyder
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// Multi-dim iface array port, sink WRITES into the iface signals, top reads.
|
||||
// Complements t_iface_array_multidim_port (which has sink reading).
|
||||
|
||||
interface simple_if;
|
||||
logic [7:0] data;
|
||||
endinterface
|
||||
|
||||
module src (simple_if b [1:0][2:0]);
|
||||
genvar gi, gj;
|
||||
generate
|
||||
for (gi = 0; gi < 2; gi++) begin : g_a
|
||||
for (gj = 0; gj < 3; gj++) begin : g_b
|
||||
initial b[gi][gj].data = 8'(gi * 3 + gj + 50);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module t;
|
||||
simple_if bus [1:0][2:0] ();
|
||||
src inst (.b(bus));
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
if (bus[0][0].data !== 8'd50) begin $write("%%Error: bus[0][0]=%0d\n", bus[0][0].data); $stop; end
|
||||
if (bus[0][1].data !== 8'd51) begin $write("%%Error: bus[0][1]=%0d\n", bus[0][1].data); $stop; end
|
||||
if (bus[0][2].data !== 8'd52) begin $write("%%Error: bus[0][2]=%0d\n", bus[0][2].data); $stop; end
|
||||
if (bus[1][0].data !== 8'd53) begin $write("%%Error: bus[1][0]=%0d\n", bus[1][0].data); $stop; end
|
||||
if (bus[1][1].data !== 8'd54) begin $write("%%Error: bus[1][1]=%0d\n", bus[1][1].data); $stop; end
|
||||
if (bus[1][2].data !== 8'd55) begin $write("%%Error: bus[1][2]=%0d\n", bus[1][2].data); $stop; end
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue