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Fix internal error on real conversion (#4447).

This commit is contained in:
Wilson Snyder 2023-08-29 18:07:23 -04:00
parent cf6566b9bc
commit 2a30bbe493
4 changed files with 11 additions and 2 deletions
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@ -28,6 +28,7 @@ Verilator 5.015 devel
* Fix coroutine handle movement during queue manipulation (#4431). [Aleksander Kiryk, Antmicro Ltd] * Fix coroutine handle movement during queue manipulation (#4431). [Aleksander Kiryk, Antmicro Ltd]
* Fix nested assignments on the LHS (#4435). [Ryszard Rozak, Antmicro Ltd] * Fix nested assignments on the LHS (#4435). [Ryszard Rozak, Antmicro Ltd]
* Fix false MULTITOP on bound interfaces (#4438). [Alex Solomatnikov] * Fix false MULTITOP on bound interfaces (#4438). [Alex Solomatnikov]
* Fix internal error on real conversion (#4447). [vdhotre-ventana]
Verilator 5.014 2023-08-06 Verilator 5.014 2023-08-06

4
src/V3Number.cpp
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@ -511,6 +511,7 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const VL_MT_STABLE {
out << "%E-bad-width-double"; // LCOV_EXCL_LINE out << "%E-bad-width-double"; // LCOV_EXCL_LINE
} else { } else {
out << toDouble(); out << toDouble();
if (toDouble() == floor(toDouble())) out << ".0";
} }
return out.str(); return out.str();
} else if (isString()) { } else if (isString()) {
@ -2217,8 +2218,9 @@ V3Number& V3Number::opAssignNonXZ(const V3Number& lhs, bool ignoreXZ) {
} else if (VL_UNLIKELY(lhs.isString())) { } else if (VL_UNLIKELY(lhs.isString())) {
// Non-compatible types, see also opAToN() // Non-compatible types, see also opAToN()
setZero(); setZero();
} else if (lhs.isDouble()) {
setDouble(lhs.toDouble());
} else { } else {
// Also handles double as is just bits
for (int bit = 0; bit < this->width(); bit++) { for (int bit = 0; bit < this->width(); bit++) {
setBit(bit, ignoreXZ ? lhs.bitIs1(bit) : lhs.bitIs(bit)); setBit(bit, ignoreXZ ? lhs.bitIs1(bit) : lhs.bitIs(bit));
} }

2
test_regress/t/t_debug_emitv.out
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@ -285,7 +285,7 @@ module Vt_debug_emitv_t;
if ((PKG_PARAM != 'sh1)) begin if ((PKG_PARAM != 'sh1)) begin
$stop; $stop;
end end
sub.r = 62; sub.r = 62.0;
$display("%g", $log10(r)); $display("%g", $log10(r));
$display("%g", $ln(r)); $display("%g", $ln(r));
$display("%g", $exp(r)); $display("%g", $exp(r));

6
test_regress/t/t_math_real.v
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@ -36,6 +36,9 @@ module t (/*AUTOARG*/
realtime uninit; realtime uninit;
initial if (uninit != 0.0) $stop; initial if (uninit != 0.0) $stop;
localparam int TWENTY = 20;
localparam real TWENDIV = $ceil((real'(TWENTY)-14.0)/2.0);
sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*); sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*);
initial begin initial begin
@ -163,6 +166,9 @@ module t (/*AUTOARG*/
r = -$sqrt(-1.0); // NaN r = -$sqrt(-1.0); // NaN
s = $sformatf("%g", r); s = $sformatf("%g", r);
`checks(s, "nan"); `checks(s, "nan");
if (real'(TWENTY) != 20.0) $stop;
if (TWENDIV != 3.0) $stop;
end end
// Test loop // Test loop