Add unsupported warning on property iff (#4848)

src/verilog.y

@@ -3360,7 +3360,8 @@ senitem<senItemp>:              // IEEE: part of event_expression, non-'OR' ','
         ;
 
 senitemVar<senItemp>:
-                idClassSel                              { $$ = new AstSenItem{$1->fileline(), VEdgeType::ET_CHANGED, $1}; }
+                idClassSel
+                        { $$ = new AstSenItem{$1->fileline(), VEdgeType::ET_CHANGED, $1}; }
         ;
 
 senitemEdge<senItemp>:          // IEEE: part of event_expression
@@ -6064,6 +6065,13 @@ property_spec<propSpecp>:               // IEEE: property_spec
                 '@' '(' senitemEdge ')' yDISABLE yIFF '(' expr ')' pexpr
                         { $$ = new AstPropSpec{$1, $3, $8, $10}; }
         |       '@' '(' senitemEdge ')' pexpr           { $$ = new AstPropSpec{$1, $3, nullptr, $5}; }
+        //                              // Disable applied after the event occurs,
+        //                              // so no existing AST can represent this
+        |       yDISABLE yIFF '(' expr ')' '@' '(' senitemEdge ')' pexpr
+                        { $$ = new AstPropSpec{$1, $8, nullptr, new AstLogOr{$1, $4, $10}};
+                          BBUNSUP($<fl>1, "Unsupported: property '(disable iff (...) @ (...)'\n"
+                                  + $<fl>1->warnMore()
+                                  + "... Suggest use property '(@(...) disable iff (...))'"); }
         //UNSUP remove above
         |       yDISABLE yIFF '(' expr ')' pexpr        { $$ = new AstPropSpec{$4->fileline(), nullptr, $4, $6}; }
         |       pexpr                                   { $$ = new AstPropSpec{$1->fileline(), nullptr, nullptr, $1}; }

test_regress/t/t_assert_iff_clk_unsup.out

@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:21: Unsupported: property '(disable iff (...) @ (...)'
+                                                    : ... Suggest use property '(@(...) disable iff (...))'
+   20 |    assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
+      |                     ^~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_assert_iff_clk_unsup.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    expect_filename => $Self->{golden_filename},
+    verilator_flags2 => ['--assert'],
+    fails => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_iff_clk_unsup.v

@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
+
+endmodule