Fix side effects for improved function/task/process purity (#6559)

include/verilated_std.sv

@@ -151,7 +151,7 @@ package std;
 
     function state status();
 `ifdef VERILATOR_TIMING
-      return state'($c(m_process, "->state()"));
+      return state'($cpure(m_process, "->state()"));
 `else
       return RUNNING;
 `endif

src/V3Const.cpp

@@ -3373,6 +3373,10 @@ class ConstVisitor final : public VNVisitor {
                     nodep->unlinkFrBack();
                 }
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
+
+                // Removed branch could contain only impurity within a function and the
+                // function could be purified
+                VIsCached::clearCacheTree();
             } else if (!AstNode::afterCommentp(nodep->thensp())
                        && !AstNode::afterCommentp(nodep->elsesp())) {
                 if (!nodep->condp()->isPure()) {

test_regress/t/t_func_purification.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_func_purification.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  initial begin
+    if (0 & func(1)) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+  function bit func(bit x);
+    if (x) begin
+      if (x) begin
+        return 1;
+      end else begin
+        $c("");
+      end
+      return 0;
+    end
+  endfunction
+endmodule