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Move testcase with real to supported 

Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
This commit is contained in:
Ryszard Rozak 2026-02-19 09:55:43 +01:00
parent f232449252
commit 27897d5ba2
2 changed files with 11 additions and 11 deletions
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11
test_regress/t/t_force_unpacked.v
View File

@ -25,6 +25,7 @@ module t (
int int_arr[-1:2][1][3];
bit [5:0] bit_arr[5];
union_t union_arr[4];
real real_arr[2][1][3];
assign bit_arr[2][3] = 1;
@ -35,18 +36,21 @@ module t (
logic_arr[0][2][-4] <= 1;
int_arr[0][0][2] <= 1;
union_arr[1].x <= 1;
real_arr[0][0][1] <= 1;
end
else if (cyc == 1) begin
`checkh(logic_arr[0][2][-4], 1);
`checkh(int_arr[0][0][2], 1);
`checkh(bit_arr[2][3], 1);
`checkh(union_arr[1].x, 1);
`checkr(real_arr[0][0][1], 1);
end
else if (cyc == 2) begin
force logic_arr[0][2][-4] = 0;
force int_arr[0][0][2] = 0;
force bit_arr[2][3] = 0;
force union_arr[1].y = 2;
force real_arr[0][0][1] = 0;
end
else if (cyc == 3) begin
`checkh(logic_arr[0][2][-4], 0);
@ -56,11 +60,14 @@ module t (
`checkh(bit_arr[2][3], 0);
`checkh(union_arr[1].x, 2);
union_arr[1].x <= 3;
`checkr(real_arr[0][0][1], 0);
real_arr[0][0][1] <= 2;
end
else if (cyc == 4) begin
`checkh(logic_arr[0][2][-4], 0);
`checkh(int_arr[0][0][2], 0);
`checkh(union_arr[1].y, 2);
`checkr(real_arr[0][0][1], 0);
end
else if (cyc == 5) begin
release logic_arr[0][2][-4];
@ -68,6 +75,7 @@ module t (
release bit_arr[2][3];
`checkh(bit_arr[2][3], 1);
release union_arr[1].x;
release real_arr[0][0][1];
end
else if (cyc == 6) begin
`checkh(logic_arr[0][2][-4], 0);
@ -77,11 +85,14 @@ module t (
`checkh(bit_arr[2][3], 1);
`checkh(union_arr[1].x, 2);
union_arr[1].y <= 4;
`checkr(real_arr[0][0][1], 0);
real_arr[0][0][1] <= 3;
end
else if (cyc == 7) begin
`checkh(logic_arr[0][2][-4], 1);
`checkh(int_arr[0][0][2], 1);
`checkh(union_arr[1].x, 4);
`checkr(real_arr[0][0][1], 3);
end
else if (cyc == 8) begin
$write("*-* All Finished *-*\n");

11
test_regress/t/t_force_unpacked_unsup.v
View File

@ -20,54 +20,43 @@ module t (
struct_t s_array[3000];
bit big_array[40][40][40];
real r_array[2];
// Test loop
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
r_array[0] <= 1;
big_array[1][2][3] <= 1;
s_array[1].x <= 1;
end
else if (cyc == 1) begin
`checkr(r_array[0], 1);
`checkr(big_array[1][2][3], 1);
`checkh(s_array[1].x, 1);
end
else if (cyc == 2) begin
force r_array[0] = 0;
force big_array[1][2][3] = 0;
force s_array[1].x = 0;
end
else if (cyc == 3) begin
`checkr(r_array[0], 0);
`checkr(big_array[1][2][3], 0);
r_array[0] <= 1;
big_array[1][2][3] <= 1;
`checkh(s_array[1].x, 0);
s_array[1].x <= 1;
end
else if (cyc == 4) begin
`checkr(r_array[0], 0);
`checkr(big_array[1][2][3], 0);
`checkh(s_array[1].x, 0);
end
else if (cyc == 5) begin
release r_array[0];
release big_array[1][2][3];
release s_array[1].x;
end
else if (cyc == 6) begin
`checkr(r_array[0], 0);
`checkr(big_array[1][2][3], 0);
r_array[0] <= 1;
big_array[1][2][3] <= 1;
`checkh(s_array[1].x, 0);
s_array[1].x <= 1;
end
else if (cyc == 7) begin
`checkr(r_array[0], 1);
`checkr(big_array[1][2][3], 1);
`checkh(s_array[1].x, 1);
end