Add DFG binToOneHot pass to generate one-hot decoders (#6096)

Somewhat commonly, there is code out there that compares an expression (or
variable) against many different constants, e.g. a one-hot decoder:

```systemverilog
  assign oneHot = {x == 3, x == 2, x == 1, x == 0};
```

If the width of the expression is sufficiently large, this can blow up
a GCC pass and take an egregious amount of memory and time to compile.

Adding a new DFG pass that will generate a cheap one-hot decoder:
to compute:

```systemverilog
  wire [$bits(x)-1:0] idx = <the expression being compared many times>
  reg tab [1<<$bits(x)] = '{default: 0};
  reg [$bits(x)-1:0] pre = '0;

  always_comb begin
    tab[pre] = 0;
    tab[idx] = 1;
    pre = idx ; // This assignment marked to avoid a false UNOPFTLAT
  end
```

We then replace the comparisons `x == CONST` with `tab[CONST]`.

This is generally performance neutral, but avoids the compile time and memory
blowup with GCC (128GB+ -> 1GB in one example).

We do not apply this if the comparisons seem to be part of a `COMPARE ?
val : COND` conditional tree, which the C++ compilers can turn into jump
tables.

This enables all XiangShan configurations from RTLMeter to now build with GCC,
so in this patch we enabled those in the nightly runs.

.github/workflows/rtlmeter.yml

@@ -72,10 +72,10 @@ jobs:
           - "VeeR-EL2:hiperf*"
           - "Vortex:mini:*"
           - "Vortex:sane:*"
-          # - "XiangShan:default-chisel3:* !*:linux"
-          # - "XiangShan:default-chisel6:* !*:linux"
+          - "XiangShan:default-chisel3:* !*:linux"
+          - "XiangShan:default-chisel6:* !*:linux"
           - "XiangShan:mini-chisel3:* !*:linux"
-          # - "XiangShan:mini-chisel6:* !*:linux"
+          - "XiangShan:mini-chisel6:* !*:linux"
           - "XuanTie-E902:*"
           - "XuanTie-E906:*"
           - "XuanTie-C906:*"