Tests: Bit extraction from non-logic types

test_regress/driver.pl

@@ -316,29 +316,29 @@ sub new {
 	atsim_flags => [split(/\s+/,"-c +sv +define+ATSIM"),
 			"+sv_dir+$self->{obj_dir}/.athdl_compile"],
 	atsim_flags2 => [],  # Overridden in some sim files
-	atsimrun_flags => [],
+	atsim_run_flags => [],
         # GHDL
 	ghdl => 0,
 	ghdl_work_dir => "$self->{obj_dir}/ghdl_compile",
 	ghdl_flags => [($::Debug?"-v":""),
 		       "--workdir=$self->{obj_dir}/ghdl_compile", ],
 	ghdl_flags2 => [],  # Overridden in some sim files
-	ghdlrun_flags => [],
+	ghdl_run_flags => [],
         # IV
 	iv => 0,
 	iv_flags => [split(/\s+/,"+define+iverilog -o $self->{obj_dir}/simiv")],
 	iv_flags2 => [],  # Overridden in some sim files
-	ivrun_flags => [],
+	iv_run_flags => [],
 	# VCS
 	vcs => 0,
 	vcs_flags => [split(/\s+/,"+vcs+lic+wait +cli -I +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")],
 	vcs_flags2 => [],  # Overridden in some sim files
-	vcsrun_flags => [split(/\s+/,"+vcs+lic_wait")],
+	vcs_run_flags => [split(/\s+/,"+vcs+lic_wait")],
 	# NC
 	nc => 0,
 	nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c ")],
 	nc_flags2 => [],  # Overridden in some sim files
-	ncrun_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")],
+	nc_run_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")],
 	# Verilator
 	vlt => 0,
 	'v3' => 0,
@@ -642,6 +642,7 @@ sub execute {
     my $self = (ref $_[0]? shift : $Self);
     return 1 if $self->errors || $self->skips;
     my %param = (%{$self}, @_);	   # Default arguments are from $self
+    #   params may be expect or {tool}_expect
     $self->oprint("Run\n");
 
     my $run_env = $param{run_env};
@@ -651,44 +652,56 @@ sub execute {
 	$self->_run(logfile=>"$self->{obj_dir}/atsim_sim.log",
 		    fails=>$param{fails},
 		    cmd=>["echo q | ".$run_env."$self->{obj_dir}/athdl_sv",
-			  @{$param{atsimrun_flags}},
+			  @{$param{atsim_run_flags}},
 			  @{$param{all_run_flags}},
-			  ]);
+		          ],
+		    %param,
+		    expect=>$param{atsim_run_expect},	# non-verilator expect isn't the same
+		    );
     }
     elsif ($param{ghdl}) {
 	$self->_run(logfile=>"$self->{obj_dir}/ghdl_sim.log",
 		    fails=>$param{fails},
 		    cmd=>[$run_env."$self->{obj_dir}/simghdl",
-			  @{$param{ghdlrun_flags}},
+			  @{$param{ghdl_run_flags}},
 			  @{$param{all_run_flags}},
-			  ]);
+		          ],
+		    %param,
+		    expect=>$param{ghdl_run_expect},	# non-verilator expect isn't the same
+		    );
     }
     elsif ($param{iv}) {
 	$self->_run(logfile=>"$self->{obj_dir}/iv_sim.log",
 		    fails=>$param{fails},
 		    cmd=>[$run_env."$self->{obj_dir}/simiv",
-			  @{$param{ivrun_flags}},
+			  @{$param{iv_run_flags}},
 			  @{$param{all_run_flags}},
-			  ]);
+		          ],
+		    %param,
+		    expect=>$param{iv_run_expect},	# non-verilator expect isn't the same
+		    );
     }
     elsif ($param{nc}) {
 	$self->_run(logfile=>"$self->{obj_dir}/nc_sim.log",
 		    fails=>$param{fails},
 		    cmd=>["echo q | ".$run_env.($ENV{VERILATOR_NCVERILOG}||"ncverilog"),
-			  @{$param{ncrun_flags}},
+			  @{$param{nc_run_flags}},
 			  @{$param{all_run_flags}},
-			  ]);
+		          ],
+		    %param,
+		    expect=>$param{nc_run_expect},	# non-verilator expect isn't the same
+		    );
     }
     elsif ($param{vcs}) {
 	#my $fh = IO::File->new(">simv.key") or die "%Error: $! simv.key,";
 	#$fh->print("quit\n"); $fh->close;
 	$self->_run(logfile=>"$self->{obj_dir}/vcs_sim.log",
 		    cmd=>["echo q | ".$run_env."./simv",
-			  @{$param{vcsrun_flags}},
+			  @{$param{vcs_run_flags}},
 			  @{$param{all_run_flags}},
 		          ],
 		    %param,
-		    expect=>undef,	# vcs expect isn't the same
+		    expect=>$param{vcs_run_expect},	# non-verilator expect isn't the same
 		    );
     }
     elsif ($param{vlt}
@@ -702,6 +715,7 @@ sub execute {
 			  @{$param{all_run_flags}},
 			  ],
 		    %param,
+		    expect=>$param{expect},		# backward compatible name
 		    );
     }
     else {

test_regress/t/t_var_types.v

@@ -113,19 +113,28 @@ module t (/*AUTOARG*/);
       // verilator lint_on UNSIGNED
 
       // Can't CHECK_ALL(d_chandle), as many operations not legal on chandles
+`ifdef VERILATOR  // else indeterminate
       if ($bits(d_chandle) !== 64) $stop;
+`endif
 
 `define CHECK_P(name,nbits) \
    if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
 
       //       name              b
       `CHECK_P(p_implicit	,96);
+      `CHECK_P(p_implicit[0]	,1 );
       `CHECK_P(p_explicit	,90);
+      `CHECK_P(p_explicit[0]	,1 );
       `CHECK_P(p_byte		,8 );
+      `CHECK_P(p_byte[0]	,1 );
       `CHECK_P(p_shortint	,16);
+      `CHECK_P(p_shortint[0]	,1 );
       `CHECK_P(p_int		,32);
+      `CHECK_P(p_int[0]		,1 );
       `CHECK_P(p_longint	,64);
+      `CHECK_P(p_longint[0]	,1 );
       `CHECK_P(p_integer	,32);
+      `CHECK_P(p_integer[0]	,1 );
       `CHECK_P(p_bit		,1 );
       `CHECK_P(p_logic		,1 );
       `CHECK_P(p_reg		,1 );
@@ -151,7 +160,9 @@ module t (/*AUTOARG*/);
       `CHECK_F(f_longint	,64,1'b1);
       `CHECK_F(f_integer	,32,1'b0);
       `CHECK_F(f_time		,64,1'b0);
+`ifdef VERILATOR  // else indeterminate
       `CHECK_F(f_chandle	,64,1'b0);
+`endif
       `CHECK_F(f_bit		,1 ,1'b1);
       `CHECK_F(f_logic		,1 ,1'b0);
       `CHECK_F(f_reg		,1 ,1'b0);

test_regress/t/t_var_types_bad.pl

@@ -0,0 +1,29 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{verilated_randReset} = 1;  # allow checking if we initialize vars to zero only when needed
+
+compile (
+	 fails=>1,
+	 expect=>
+'%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: d_bitz
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: d_logicz
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: d_regz
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: d_real
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: d_realtime
+%Error: t/t_var_types_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension
+%Error: Exiting due to.*',
+	 );
+
+ok(1);
+1;

test_regress/t/t_var_types_bad.v

@@ -0,0 +1,60 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   // IEEE: integer_atom_type
+   byte		d_byte;
+   shortint	d_shortint;
+   int		d_int;
+   longint	d_longint;
+   integer	d_integer;
+   time		d_time;
+   chandle	d_chandle;
+
+   // IEEE: integer_atom_type
+   bit		d_bit;
+   logic	d_logic;
+   reg		d_reg;
+
+   bit [0:0]	d_bit1;
+   logic [0:0]	d_logic1;
+   reg [0:0]	d_reg1;
+
+   bit		d_bitz;
+   logic	d_logicz;
+   reg		d_regz;
+
+   // IEEE: non_integer_type
+   //UNSUP shortreal	d_shortreal;
+   real		d_real;
+   realtime	d_realtime;
+
+   initial begin
+      // below errors might cause spurious warnings
+      // verilator lint_off WIDTH
+      d_bitz[0] = 1'b1;		// Illegal range
+      d_logicz[0] = 1'b1;	// Illegal range
+      d_regz[0] = 1'b1;		// Illegal range
+
+`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
+      d_chandle[0] = 1'b1;	// Illegal
+`endif
+      d_real[0] = 1'b1;		// Illegal
+      d_realtime[0] = 1'b1;	// Illegal
+      // verilator lint_on WIDTH
+
+      d_byte[0] = 1'b1;		// OK
+      d_shortint[0] = 1'b1;	// OK
+      d_int[0] = 1'b1;		// OK
+      d_longint[0] = 1'b1;	// OK
+      d_integer[0] = 1'b1;	// OK
+      d_time[0] = 1'b1;		// OK
+
+      d_bit1[0] = 1'b1;		// OK
+      d_logic1[0] = 1'b1;	// OK
+      d_reg1[0] = 1'b1;		// OK
+   end
+endmodule