Fix pullup/pulldown to create implicit wires.

src/V3LinkDot.cpp

@@ -1709,6 +1709,13 @@ private:
         }
         iterateChildren(nodep);
     }
+    void visit(AstPull* nodep) override {
+        // Deal with implicit definitions
+        // We used to nodep->allowImplicit() here, but it turns out
+        // normal "assigns" can also make implicit wires.  Yuk.
+        pinImplicitExprRecurse(nodep->lhsp());
+        iterateChildren(nodep);
+    }
     void visit(AstTypedefFwd* nodep) override {
         VSymEnt* const foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->name());
         if (!foundp && v3Global.opt.pedantic()

test_regress/t/t_tri_pull_implicit.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_tri_pull_implicit.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   // verilator lint_off IMPLICIT
+   pulldown (pd);
+   pullup (pu);
+
+   initial begin
+      if (pd != 0) $stop;
+      if (pu != 1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule