Tests: Add t_var_rsvd_port test

test_regress/t/t_var_rsvd_bad.pl

@@ -7,11 +7,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 
+top_filename("t/t_var_rsvd_port.v");
+
 compile (
 	 fails=>$Self->{v3},
 	 expect=>
-q{%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ common word: 'bool'
+q{%Error-SYMRSVDWORD: t/t_var_rsvd_port.v:\d+: Symbol matches C\+\+ common word: 'bool'
-%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ reserved word: 'switch'
+%Error-SYMRSVDWORD: t/t_var_rsvd_port.v:\d+: Symbol matches C\+\+ reserved word: 'switch'
 %Error: Exiting due to.*},
 	 );
 

test_regress/t/t_var_rsvd_port.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 verilator_flags2=>["-Wno-SYMRSVDWORD"],
+	 );
+
+execute();
+
+ok(1);
+1;

test_regress/t/t_var_rsvd_port.v

@@ -13,6 +13,8 @@ module t (/*AUTOARG*/
    reg  vector;	// OK, as not public
    reg  switch /*verilator public*/;	// Bad
 
-   initial $stop;
+   initial begin
-
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
 endmodule