Signed-off-by: Artur Bieniek <abieniek@internships.antmicro.com>
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@ -147,7 +147,7 @@ private:
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// AstVar::user1p -> ForceComponentsVar* instance (via m_forceComponentsVar)
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// AstVarScope::user1p -> ForceComponentsVarScope* instance (via m_forceComponentsVarScope)
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// AstVarRef::user2 -> Flag indicating not to replace reference
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// AstVarScope::user3p -> AstNodeExpr*, the RHS expression
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// AstVarScope::user3p -> AstAssign*, the assignment <lhs>__VforceVal = <rhs>
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const VNUser1InUse m_user1InUse;
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const VNUser2InUse m_user2InUse;
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const VNUser3InUse m_user3InUse;
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@ -197,11 +197,9 @@ public:
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ForceComponentsVarScope* tryGetForceComponents(AstVarRef* nodep) const {
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return m_forceComponentsVarScope.tryGet(nodep->varScopep());
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}
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void setValVscpRhsExpr(AstVarScope* valVscp, AstNodeExpr* rhsExpr) {
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valVscp->user3p(rhsExpr);
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}
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AstNodeExpr* getValVscpRhsExpr(AstVarScope* valVscp) const {
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return VN_CAST(valVscp->user3p(), NodeExpr);
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void setValVscpAssign(AstVarScope* valVscp, AstAssign* rhsExpr) { valVscp->user3p(rhsExpr); }
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AstAssign* getValVscpAssign(AstVarScope* valVscp) const {
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return VN_CAST(valVscp->user3p(), Assign);
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}
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};
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@ -249,9 +247,9 @@ class ForceConvertVisitor final : public VNVisitor {
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// Set corresponding value signals to the forced value
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AstAssign* const setValp
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= new AstAssign{flp, lhsp->cloneTreePure(false), rhsp->cloneTreePure(false)};
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transformWritenVarScopes(setValp->lhsp(), [this, rhsp](AstVarScope* vscp) {
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transformWritenVarScopes(setValp->lhsp(), [this, rhsp, setValp](AstVarScope* vscp) {
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AstVarScope* const valVscp = m_state.getForceComponents(vscp).m_valVscp;
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m_state.setValVscpRhsExpr(valVscp, rhsp);
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m_state.setValVscpAssign(valVscp, setValp);
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rhsp->foreach([valVscp, this](AstVarRef* refp) { m_state.addValVscp(refp, valVscp); });
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return valVscp;
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});
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@ -393,15 +391,15 @@ class ForceReplaceVisitor final : public VNVisitor {
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if (!m_state.getValVscps(nodep)) break;
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for (AstVarScope* const valVscp : *m_state.getValVscps(nodep)) {
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FileLine* const flp = nodep->fileline();
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AstVarRef* const valp = new AstVarRef{flp, valVscp, VAccess::WRITE};
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AstNodeExpr* rhsp = m_state.getValVscpRhsExpr(valVscp);
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UASSERT_OBJ(rhsp, flp, "RHS of force/release must be an AstNodeExpr");
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rhsp = rhsp->cloneTreePure(false);
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AstAssign* assignp = m_state.getValVscpAssign(valVscp);
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UASSERT_OBJ(assignp, flp, "Missing stored assignment for forced valVscp");
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ForceState::markNonReplaceable(valp);
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rhsp->foreach([](AstVarRef* refp) { ForceState::markNonReplaceable(refp); });
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assignp = assignp->cloneTreePure(false);
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m_stmtp->addNextHere(new AstAssign{flp, valp, rhsp});
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assignp->rhsp()->foreach(
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[](AstVarRef* refp) { ForceState::markNonReplaceable(refp); });
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m_stmtp->addNextHere(assignp);
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}
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break;
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}
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,31 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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typedef struct packed {
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logic sig1;
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logic sig2;
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logic not_forced;
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} s1;
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module t(clk);
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input clk;
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s1 s1inst;
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logic a = 1'b0;
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logic b;
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initial force s1inst.sig1 = a;
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always @(posedge clk) begin
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force s1inst.sig2 = 1'b1;
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force s1inst.sig1 = b;
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`checkh(s1inst.sig1, b);
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`checkh(s1inst.sig2, 1'b1);
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$finish;
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end
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endmodule
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