Fix preprocessor stringify of undefined macro.

Changes

@@ -21,6 +21,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix flushCall for backward compatibility (#2580). [chenguokai]
 
+****  Fix preprocessor stringify of undefined macro. [Martin Whitaker]
+
 
 * Verilator 4.100 2020-09-07
 

src/V3PreProc.cpp

@@ -1401,7 +1401,10 @@ int V3PreProcImp::getStateToken() {
                 if (m_off) {
                     goto next_tok;
                 } else {
-                    return VP_TEXT;
+                    // We want final text of `name, but that would cause
+                    // recursion, so use a special character to get it through
+                    unputDefrefString(string("`\032") + name);
+                    goto next_tok;
                 }
             } else {
                 string params = defParams(name);

test_regress/t/t_preproc.out

@@ -937,6 +937,12 @@ endmodule
  
  
  
+"`NOT_DEFINED_STR"
+
+`line 640 "t/t_preproc.v" 0
+ 
+ 
+   
 predef 0 0
 predef 1 1
 predef 2 2
@@ -956,4 +962,4 @@ predef 2 2
  
  
 
-`line 657 "t/t_preproc.v" 2
+`line 662 "t/t_preproc.v" 2

test_regress/t/t_preproc.v

@@ -632,6 +632,11 @@ module pcc2_cfg;
   endgenerate
 endmodule
 
+//======================================================================
+// Verilog-Perl bug1668
+`define stringify(text) `"text`"
+`stringify(`NOT_DEFINED_STR)
+
 //======================================================================
 // IEEE mandated predefines
 `undefineall  // undefineall should have no effect on these

test_regress/t/t_preproc_comments.out

@@ -940,6 +940,12 @@ endmodule
 
 `line 635 "t/t_preproc.v" 0
 //====================================================================== 
+// Verilog-Perl bug1668 
+ 
+"`NOT_DEFINED_STR"
+
+`line 640 "t/t_preproc.v" 0
+//====================================================================== 
 // IEEE mandated predefines 
   // undefineall should have no effect on these 
 predef 0 0
@@ -961,4 +967,4 @@ predef 2 2
 // After `undefineall above, for testing --dump-defines 
  
 
-`line 657 "t/t_preproc.v" 2
+`line 662 "t/t_preproc.v" 2

test_regress/t/t_preproc_str_undef.out

@@ -0,0 +1,4 @@
+`PREFIX_my_suffix
+`PREFIX_my_suffix
+my_prefix_suffix
+*-* All Finished *-*

test_regress/t/t_preproc_str_undef.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_preproc_str_undef.v

@@ -0,0 +1,21 @@
+`define PREFIX_        my_prefix_
+`define SUFFIX          my_suffix
+`define PREFIX_SUFFIX   my_prefix_suffix
+`define name1           `PREFIX``_```SUFFIX
+`define name2(p,s)      p``_``s
+`define name3(p)        ```p``_SUFFIX
+`define stringify(text) `"text`"
+
+module t();
+   initial begin
+      // Another simulator gives:
+      //  `PREFIX_my_suffix
+      //  `name2(`PREFIX, my_suffix)
+      //  `name3(PREFIX)
+      $display(`stringify(`name1));
+      $display(`stringify(`name2(`PREFIX, `SUFFIX)));
+      $display(`stringify(`name3(PREFIX)));
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_preproc_ttempty.out

@@ -1 +0,0 @@
- `TARGET_PACKAGE