luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Tests: Rename test of last commit

This commit is contained in:
Wilson Snyder 2022-12-23 13:12:21 -05:00
parent d5a18c99fe
commit 1f58f48c05
2 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
test_regress/t/t_0.pl → test_regress/t/t_func_sel.pl
View File

3
test_regress/t/t_0.v → test_regress/t/t_func_sel.v
View File

@ -32,8 +32,10 @@ module t(/*AUTOARG*/
// Test loop // Test loop
always @ (posedge clk) begin always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x in=%x out=%x\n", $write("[%0t] cyc==%0d crc=%x result=%x in=%x out=%x\n",
$time, cyc, crc, result, in, out); $time, cyc, crc, result, in, out);
`endif
cyc <= cyc + 1; cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[127:1], 1'b0} + result; sum <= {sum[127:1], 1'b0} + result;
@ -54,6 +56,7 @@ module t(/*AUTOARG*/
function [W-1:0] reverse(input [W-1:0] val); function [W-1:0] reverse(input [W-1:0] val);
integer i; integer i;
// Bug workaround: reverse = '0;
for (i = 0; i < W; i = i + 1) for (i = 0; i < W; i = i + 1)
reverse[W-1-i] = val[i]; reverse[W-1-i] = val[i];
endfunction endfunction