Fix -Wno-UNOPTFLAT change detection with 64-bits, bug762.

Changes

@@ -1,4 +1,4 @@
-Revision history for Verilator
+overRevision history for Verilator
 
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
@@ -44,6 +44,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix change detection error on unions, bug758. [Jie Xu]
 
+****  Fix -Wno-UNOPTFLAT change detection with 64-bits, bug762. [Clifford Wolf]
+
 ****  Fix Mac OS-X test issues. [Holger Waechtler]
 
 ****  Fix C++-2011 warnings.

src/V3Changed.cpp

@@ -144,7 +144,7 @@ private:
 	if (!scopep) nodep->v3fatalSrc("No scope found on top level, perhaps you have no statements?\n");
 	m_scopetopp = scopep;
 	// Create change detection function
-	m_chgFuncp = new AstCFunc(nodep->fileline(), "_change_request", scopep, "IData");
+	m_chgFuncp = new AstCFunc(nodep->fileline(), "_change_request", scopep, "QData");
 	m_chgFuncp->argTypes(EmitCBaseVisitor::symClassVar());
 	m_chgFuncp->symProlog(true);
 	m_chgFuncp->declPrivate(true);

src/V3EmitC.cpp

@@ -832,7 +832,7 @@ class EmitCImp : EmitCStmts {
 
     void emitChangeDet() {
 	puts("// Change detection\n");
-	puts("IData __req = false;  // Logically a bool\n");  // But not because it results in faster code
+	puts("QData __req = false;  // Logically a bool\n");  // But not because it results in faster code
 	bool gotOne = false;
 	for (vector<AstChangeDet*>::iterator it = m_blkChangeDetVec.begin();
 	     it != m_blkChangeDetVec.end(); ++it) {
@@ -1663,7 +1663,7 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
     puts("// Evaluate till stable\n");
     puts("VL_DEBUG_IF(VL_PRINTF(\"\\n----TOP Evaluate "+modClassName(modp)+"::eval\\n\"); );\n");
     puts("int __VclockLoop = 0;\n");
-    puts("IData __Vchange=1;\n");
+    puts("QData __Vchange=1;\n");
     puts("while (VL_LIKELY(__Vchange)) {\n");
     puts(    "VL_DEBUG_IF(VL_PRINTF(\" Clock loop\\n\"););\n");
     puts(    "vlSymsp->__Vm_activity = true;\n");
@@ -1681,7 +1681,7 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
     puts("_eval_initial(vlSymsp);\n");
     puts(    "vlSymsp->__Vm_activity = true;\n");
     puts(    "int __VclockLoop = 0;\n");
-    puts(    "IData __Vchange=1;\n");
+    puts(    "QData __Vchange=1;\n");
     puts(    "while (VL_LIKELY(__Vchange)) {\n");
     puts(        "_eval_settle(vlSymsp);\n");
     puts(        "_eval(vlSymsp);\n");

test_regress/t/t_order_quad.cpp

@@ -0,0 +1,50 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+#include <verilated.h>
+#include "Vt_order_quad.h"
+
+//======================================================================
+
+unsigned int main_time = 0;
+
+double sc_time_stamp () {
+    return main_time;
+}
+
+VM_PREFIX* topp = NULL;
+bool fail = false;
+
+void check (QData got, QData exp) {
+    if (got != exp) {
+	VL_PRINTF("%%Error: got=0x%" VL_PRI64 "x exp=0x%" VL_PRI64 "x\n", got, exp);
+	fail = true;
+    }
+}
+
+int main (int argc, char *argv[]) {
+    topp = new VM_PREFIX;
+
+    Verilated::debug(0);
+
+    topp->a0 = 0;
+    topp->eval();
+    check (topp->y, VL_ULL(0x0));
+
+    topp->a0 = 15;
+    topp->eval();
+    check (topp->y, VL_ULL(0x3c00000000));
+
+    topp->final();
+    if (!fail) {
+	VL_PRINTF("*-* All Finished *-*\n");
+	topp->final();
+    } else {
+	vl_fatal(__FILE__,__LINE__,"top", "Unexpected results\n");
+    }
+    return 0;
+}

test_regress/t/t_order_quad.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_order_quad.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+//bug 762
+module t(a0, y);
+   input [3:0] a0;
+   output [44:0] y;
+
+   assign y[40] = 0;
+   assign y[30] = 0;
+   // verilator lint_off UNOPTFLAT
+   assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 };
+   
+endmodule