Merge from master
This commit is contained in:
commit
1f04d17e77
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@ -23,6 +23,7 @@ dddrun*
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doxygen-doc
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gdbrun*
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gmon.out
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ncverilog.history
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internals.txt
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verilator.txt
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verilator_bin*
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2
Changes
2
Changes
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@ -13,7 +13,7 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix internals to avoid 'using namespace std'.
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* Verilator 3.921 devel
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* Verilator 3.922 2018-03-17
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** Support IEEE 1800-2017 as default language.
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@ -34,6 +34,7 @@ verilator.pc$
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verilator_bin.*
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verilator_coverage_bin.*
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.vcsmx_rebuild$
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ncverilog.history
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autom4te\.cache/
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nodist/
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/simv$
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@ -49,8 +49,7 @@ private:
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AstUser1InUse m_inuser1;
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// STATE
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AstNodeModule* m_modp; // Current module
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AstCell* m_cellp; // Current cell
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AstCell* m_cellp; // Current cell
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static int debug() {
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static int level = -1;
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@ -60,13 +59,6 @@ private:
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//int m_debug; int debug() { return m_debug; }
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// VISITORS
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virtual void visit(AstNodeModule* nodep) {
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UINFO(4," MOD "<<nodep<<endl);
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//if (nodep->name() == "t_chg") m_debug = 9; else m_debug=0;
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m_modp = nodep;
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nodep->iterateChildren(*this);
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m_modp = NULL;
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}
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virtual void visit(AstCell* nodep) {
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UINFO(4," CELL "<<nodep<<endl);
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m_cellp = nodep;
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@ -96,7 +88,7 @@ private:
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} else if (nodep->modVarp()->isOutput()) {
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AstNode* rhsp = new AstVarXRef (exprp->fileline(), nodep->modVarp(), m_cellp->name(), false);
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AstAssignW* assp = new AstAssignW (exprp->fileline(), exprp, rhsp);
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m_modp->addStmtp(assp);
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m_cellp->addNextHere(assp);
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} else if (nodep->modVarp()->isInput()) {
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// Don't bother moving constants now,
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// we'll be pushing the const down to the cell soon enough.
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@ -104,7 +96,7 @@ private:
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(exprp->fileline(),
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new AstVarXRef(exprp->fileline(), nodep->modVarp(), m_cellp->name(), true),
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exprp);
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m_modp->addStmtp(assp);
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m_cellp->addNextHere(assp);
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if (debug()>=9) assp->dumpTree(cout," _new: ");
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} else if (nodep->modVarp()->isIfaceRef()
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|| (VN_IS(nodep->modVarp()->subDTypep(), UnpackArrayDType)
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@ -115,7 +107,7 @@ private:
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const AstVarXRef* xrefp = VN_CAST(exprp, VarXRef);
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if (!refp && !xrefp) exprp->v3fatalSrc("Interfaces: Pin is not connected to a VarRef or VarXRef");
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AstAssignVarScope* assp = new AstAssignVarScope(exprp->fileline(), lhsp, exprp);
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m_modp->addStmtp(assp);
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m_cellp->addNextHere(assp);
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} else {
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nodep->v3error("Assigned pin is neither input nor output");
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}
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@ -145,7 +137,6 @@ private:
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public:
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// CONSTUCTORS
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explicit InstVisitor(AstNetlist* nodep) {
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m_modp=NULL;
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m_cellp=NULL;
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//
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nodep->accept(*this);
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@ -53,8 +53,9 @@ private:
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// TYPES
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typedef vl_unordered_map<AstPackage*, AstScope*> PackageScopeMap;
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typedef vl_unordered_map<std::pair<AstVar*, AstScope*>, AstVarScope*> VarScopeMap;
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typedef vl_unordered_set<std::pair<AstVarRef*, AstScope*> > VarRefScopeSet;
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// These cannot be unordered unless make a specialized hashing pair (gcc-8)
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typedef std::map<std::pair<AstVar*, AstScope*>, AstVarScope*> VarScopeMap;
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typedef std::set<std::pair<AstVarRef*, AstScope*> > VarRefScopeSet;
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// STATE, inside processing a single module
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AstNodeModule* m_modp; // Current module
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@ -978,7 +978,12 @@ sub _run {
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flush STDERR;
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if (!$param{fails} && $status) {
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$self->error("Exec of $param{cmd}[0] failed\n");
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my $firstline = "";
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if (my $fh = IO::File->new("<$param{logfile}")) {
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$firstline = $fh->getline;
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chomp $firstline;
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}
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$self->error("Exec of $param{cmd}[0] failed: $firstline\n");
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}
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if ($param{fails} && $status) {
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print "(Exec expected to fail, and did.)\n";
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@ -15,7 +15,7 @@ compile (
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# Override default flags
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v_flags => [''],
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v_other_filenames => ["t_preproc_persist2.v"],
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verilator_flags => ["-E -P +incdir+t"],
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verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ],
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verilator_flags2 => ['',],
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verilator_flags3 => ['',],
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verilator_make_gcc => 0,
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@ -14,7 +14,7 @@ my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp";
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compile (
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# Override default flags
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v_flags => [''],
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verilator_flags => ["-E -P +incdir+t"],
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verilator_flags => ["-E -P +incdir+t -Mdir $Self->{obj_dir}", ],
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verilator_flags2 => ['',],
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verilator_flags3 => ['',],
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verilator_make_gcc => 0,
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