Update preprocessor to match next Verilog-Perl version.

Fix preprocessor preservation of newlines across macro substitutions.
Fix preprocessor stringification of nested macros.
Fix preprocessor whitespace on define arguments
This commit is contained in:
Wilson Snyder
2010-07-10 18:30:16 -04:00
parent f3704f4c05
commit 1e938d0e90
14 changed files with 1304 additions and 351 deletions
+386 -191
View File
File diff suppressed because it is too large Load Diff