Fix corner case bugs in module and variable inlining (#6322)

There were a couple corner case bugs in V3Inline, and one in Dfg when
dealing with inlining of modules/variables.

V3Inline:
- Invalid code generated when inlining an input that also had an
  assignment to it (Throws an ASSIGNIN, but this is sometimes reasonable
  to do, e.g. hiererchical reference to an unonnected input port)
- Inlining (aliasing) publicly writeable input port.
- Inlining forcable port connected to constant.

Dfg:
- Inining publicly writeable variables

The tests that cover these are the same and fixing one will trigger the
other bug, so fixing them all in one go. Also cleanup V3Inline to be less
out of order and rely less on unique APIs only used by V3Inine (will
remove those in follow up patch).

Small step towards #6280.

src/V3Sched.cpp

@@ -743,7 +743,7 @@ const TriggerKit createTriggers(AstNetlist* netlistp, AstCFunc* const initFuncp,
         ss << "@(";
         V3EmitV::verilogForTree(senItemp, ss);
         ss << ")";
-        addDebug(triggerNumber, ss.str());
+        addDebug(triggerNumber, VString::quoteBackslash(ss.str()));
 
         //
         ++triggerNumber;