Fix simulation error when inputs and MULTIDRIVEN, bug634.
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Wilson Snyder
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d581582339
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1bea845ceb
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@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Add --pins-sc-uint and --pins-sc-biguint, bug638. [Alex Hornung]
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**** Fix simulation error when inputs and MULTIDRIVEN, bug634. [Ted Campbell]
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**** Fix module resolution with __, bug631. [Jason McMullan]
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@ -375,8 +375,10 @@ private:
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void processBrokeLoop();
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#endif
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void processCircular();
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typedef deque<OrderEitherVertex*> VertexVec;
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void processInputs();
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void processInputsIterate(OrderEitherVertex* vertexp);
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void processInputsInIterate(OrderEitherVertex* vertexp, VertexVec& todoVec);
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void processInputsOutIterate(OrderEitherVertex* vertexp, VertexVec& todoVec);
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void processSensitive();
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void processDomains();
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void processDomainsIterate(OrderEitherVertex* vertexp);
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@ -1059,28 +1061,33 @@ void OrderVisitor::processBrokeLoop() {
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// Clock propagation
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void OrderVisitor::processInputs() {
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m_graph.userClearVertices(); // Vertex::user() // true if processed
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m_graph.userClearVertices(); // Vertex::user() // 1 if input recursed, 2 if marked as input, 3 if out-edges recursed
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// Start at input vertex, process from input-to-output order
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VertexVec todoVec; // List of newly-input marked vectors we need to process
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todoVec.push_front(m_inputsVxp);
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m_inputsVxp->isFromInput(true); // By definition
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processInputsIterate(m_inputsVxp);
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while (!todoVec.empty()) {
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OrderEitherVertex* vertexp = todoVec.back(); todoVec.pop_back();
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processInputsOutIterate(vertexp, todoVec);
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}
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}
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void OrderVisitor::processInputsIterate(OrderEitherVertex* vertexp) {
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void OrderVisitor::processInputsInIterate(OrderEitherVertex* vertexp, VertexVec& todoVec) {
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// Propagate PrimaryIn through simple assignments
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if (vertexp->user()) return; // Already processed
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if (0 && debug()>=9) {
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UINFO(9," InIt "<<vertexp<<endl);
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UINFO(9," InIIter "<<vertexp<<endl);
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if (OrderLogicVertex* vvertexp = dynamic_cast<OrderLogicVertex*>(vertexp)) {
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vvertexp->nodep()->dumpTree(cout,"- TT: ");
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}
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}
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vertexp->user(true); // Processing
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vertexp->user(1); // Processing
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// First handle all inputs to this vertex, in most cases they'll be already processed earlier
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// Also, determine if this vertex is an input
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int inonly = 1; // 0=no, 1=maybe, 2=yes until a no
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for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep=edgep->inNextp()) {
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OrderEitherVertex* frVertexp = (OrderEitherVertex*)edgep->fromp();
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processInputsIterate(frVertexp);
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processInputsInIterate(frVertexp, todoVec);
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if (frVertexp->isFromInput()) {
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if (inonly==1) inonly = 2;
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} else if (dynamic_cast<OrderVarPostVertex*>(frVertexp)) {
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@ -1091,20 +1098,38 @@ void OrderVisitor::processInputsIterate(OrderEitherVertex* vertexp) {
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break;
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}
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}
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if (inonly == 2) { // Set it. Note may have already been set earlier, too
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if (inonly == 2 && vertexp->user()<2) { // Set it. Note may have already been set earlier, too
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UINFO(9," Input reassignment: "<<vertexp<<endl);
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vertexp->isFromInput(true);
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vertexp->user(2); // 2 means on list
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// Can't work on out-edges of a node we know is an input immediately,
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// as it might visit other nodes before their input state is resolved.
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// So push to list and work on it later when all in-edges known resolved
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todoVec.push_back(vertexp);
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}
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// If we're still an input, process all targets of this vertex
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if (vertexp->isFromInput()) {
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//UINFO(9," InIdone "<<vertexp<<endl);
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}
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void OrderVisitor::processInputsOutIterate(OrderEitherVertex* vertexp, VertexVec& todoVec) {
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if (vertexp->user()==3) return; // Already out processed
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//UINFO(9," InOIter "<<vertexp<<endl);
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// First make sure input path is fully recursed
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processInputsInIterate(vertexp, todoVec);
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// Propagate PrimaryIn through simple assignments
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if (!vertexp->isFromInput()) v3fatalSrc("processInputsOutIterate only for input marked vertexes");
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vertexp->user(3); // out-edges processed
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{
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// Propagate PrimaryIn through simple assignments, followint target of vertex
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for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
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OrderEitherVertex* toVertexp = (OrderEitherVertex*)edgep->top();
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if (OrderVarStdVertex* vvertexp = dynamic_cast<OrderVarStdVertex*>(toVertexp)) {
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processInputsIterate(vvertexp);
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processInputsInIterate(vvertexp, todoVec);
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}
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if (OrderLogicVertex* vvertexp = dynamic_cast<OrderLogicVertex*>(toVertexp)) {
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if (vvertexp->nodep()->castNodeAssign()) {
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processInputsIterate(vvertexp);
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processInputsInIterate(vvertexp, todoVec);
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}
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}
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}
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@ -0,0 +1,56 @@
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Ted Campbell.
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#include "Vt_order_multidriven.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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Vt_order_multidriven * vcore;
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VerilatedVcdC * vcd;
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vluint64_t vtime;
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#define PHASE_90
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static void half_cycle( int clk ) {
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if ( clk & 1 ) vcore->i_clk_wr = !vcore->i_clk_wr;
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if ( clk & 2 ) vcore->i_clk_rd = !vcore->i_clk_rd;
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vtime += 10 / 2;
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vcore->eval();
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vcore->eval();
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vcd->dump( vtime );
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}
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static void cycle() {
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#ifdef PHASE_90
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half_cycle( 1 );
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half_cycle( 2 );
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half_cycle( 1 );
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half_cycle( 2 );
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#else
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half_cycle( 3 );
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half_cycle( 3 );
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#endif
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}
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int main() {
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Verilated::traceEverOn( true );
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vcore = new Vt_order_multidriven;
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vcd = new VerilatedVcdC;
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vcore->trace( vcd, 99 );
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vcd->open( "obj_dir/t_order_multidriven/sim.vcd" );
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vcore->i_clk_wr = 0;
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vcore->i_clk_rd = 0;
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for ( int i = 0; i < 256; ++i )
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cycle( );
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vcd->close( );
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printf("*-* All Finished *-*\n");
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}
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@ -0,0 +1,23 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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$Self->{vlt} or $Self->skip("Verilator only test");
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compile (
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make_top_shell => 0,
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make_main => 0,
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v_flags2 => ["--trace --exe $Self->{t_dir}/t_order_multidriven.cpp"],
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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@ -0,0 +1,192 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Ted Campbell.
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//With MULTI_CLK defined shows bug, without it is hidden
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`define MULTI_CLK
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//bug634
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module t (
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input i_clk_wr,
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input i_clk_rd
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);
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wire wr$wen;
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wire [7:0] wr$addr;
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wire [7:0] wr$wdata;
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wire [7:0] wr$rdata;
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wire rd$wen;
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wire [7:0] rd$addr;
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wire [7:0] rd$wdata;
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wire [7:0] rd$rdata;
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wire clk_wr;
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wire clk_rd;
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`ifdef MULTI_CLK
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assign clk_wr = i_clk_wr;
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assign clk_rd = i_clk_rd;
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`else
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assign clk_wr = i_clk_wr;
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assign clk_rd = i_clk_wr;
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`endif
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FooWr u_wr (
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.i_clk ( clk_wr ),
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.o_wen ( wr$wen ),
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.o_addr ( wr$addr ),
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.o_wdata ( wr$wdata ),
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.i_rdata ( wr$rdata )
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);
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FooRd u_rd (
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.i_clk ( clk_rd ),
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.o_wen ( rd$wen ),
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.o_addr ( rd$addr ),
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.o_wdata ( rd$wdata ),
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.i_rdata ( rd$rdata )
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);
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FooMem u_mem (
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.iv_clk ( {clk_wr, clk_rd } ),
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.iv_wen ( {wr$wen, rd$wen } ),
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.iv_addr ( {wr$addr, rd$addr } ),
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.iv_wdata ( {wr$wdata,rd$wdata} ),
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.ov_rdata ( {wr$rdata,rd$rdata} )
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);
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endmodule
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// Memory Writer
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module FooWr(
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input i_clk,
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output o_wen,
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output [7:0] o_addr,
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output [7:0] o_wdata,
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input [7:0] i_rdata
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);
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reg [7:0] cnt = 0;
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// Count [0,200]
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always @( posedge i_clk )
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if ( cnt < 8'd50 )
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cnt <= cnt + 8'd1;
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// Write addr in (10,30) if even
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assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
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assign o_addr = cnt;
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assign o_wdata = cnt;
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endmodule
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// Memory Reader
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module FooRd(
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input i_clk,
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output o_wen,
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output [7:0] o_addr,
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output [7:0] o_wdata,
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input [7:0] i_rdata
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);
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reg [7:0] cnt = 0;
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reg [7:0] addr_r;
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reg en_r;
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// Count [0,200]
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always @( posedge i_clk )
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if ( cnt < 8'd200 )
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cnt <= cnt + 8'd1;
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// Read data
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assign o_wen = 0;
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assign o_addr = cnt - 8'd100;
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// Track issued read
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always @( posedge i_clk )
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begin
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addr_r <= o_addr;
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en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
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end
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// Display to console 100 cycles after writer
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always @( negedge i_clk )
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if ( en_r ) begin
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`ifdef TEST_VERBOSE
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$display( "MEM[%x] == %x", addr_r, i_rdata );
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`endif
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if (addr_r != i_rdata) $stop;
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end
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endmodule
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// Multi-port memory abstraction
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module FooMem(
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input [2 -1:0] iv_clk,
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input [2 -1:0] iv_wen,
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input [2*8-1:0] iv_addr,
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input [2*8-1:0] iv_wdata,
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output [2*8-1:0] ov_rdata
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);
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FooMemImpl u_impl (
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.a_clk ( iv_clk [0*1+:1] ),
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.a_wen ( iv_wen [0*1+:1] ),
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.a_addr ( iv_addr [0*8+:8] ),
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.a_wdata ( iv_wdata[0*8+:8] ),
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.a_rdata ( ov_rdata[0*8+:8] ),
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.b_clk ( iv_clk [1*1+:1] ),
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.b_wen ( iv_wen [1*1+:1] ),
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.b_addr ( iv_addr [1*8+:8] ),
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.b_wdata ( iv_wdata[1*8+:8] ),
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.b_rdata ( ov_rdata[1*8+:8] )
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);
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endmodule
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// Dual-Port L1 Memory Implementation
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module FooMemImpl(
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input a_clk,
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input a_wen,
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input [7:0] a_addr,
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input [7:0] a_wdata,
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output [7:0] a_rdata,
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input b_clk,
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input b_wen,
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input [7:0] b_addr,
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input [7:0] b_wdata,
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output [7:0] b_rdata
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);
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/* verilator lint_off MULTIDRIVEN */
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reg [7:0] mem[0:255];
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/* verilator lint_on MULTIDRIVEN */
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always @( posedge a_clk )
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if ( a_wen )
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mem[a_addr] <= a_wdata;
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always @( posedge b_clk )
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if ( b_wen )
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mem[b_addr] <= b_wdata;
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always @( posedge a_clk )
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a_rdata <= mem[a_addr];
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always @( posedge b_clk )
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b_rdata <= mem[b_addr];
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endmodule
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