Drop redundant width sets and cover weak always low-bound rejection

src/V3AssertNfa.cpp

@@ -1786,19 +1786,16 @@ public:
                 pendingp = svp;
             } else {
                 pendingp = new AstLogOr{flp, pendingp, svp};
-                pendingp->dtypeSetBit();
             }
         }
         if (pendingp) {
             AstCExpr* const assertOnp
                 = new AstCExpr{flp, AstCExpr::Pure{}, "vlSymsp->_vm_contextp__->assertOn()", 1};
-            assertOnp->dtypeSetBit();
             AstNodeExpr* const condp = new AstLogAnd{flp, assertOnp, pendingp};
-            condp->dtypeSetBit();
             AstDisplay* const dispp
                 = new AstDisplay{flp, VDisplayType::DT_ERROR, "", nullptr, nullptr};
             dispp->fmtp()->timeunit(m_modp->timeunit());
-            AstNodeStmt* firep = dispp;
+            AstNodeStmt* const firep = dispp;
             if (v3Global.opt.stopFail()) firep->addNext(new AstStop{flp, false});
             m_modp->addStmtsp(new AstFinal{flp, new AstIf{flp, condp, firep}});
         }

test_regress/t/t_assert_always_unbounded_bad.out

@@ -7,4 +7,8 @@
                                                : ... note: In instance 't'
    14 |   assert property (@(posedge clk) s_always [2:$] a);
       |                                   ^~~~~~~~
+%Error: t/t_assert_always_unbounded_bad.v:18:35: always range low bound must be a constant expression (IEEE 1800-2023 16.12.11)
+                                               : ... note: In instance 't'
+   18 |   assert property (@(posedge clk) always [$:5] a);
+      |                                   ^~~~~~
 %Error: Exiting due to

test_regress/t/t_assert_always_unbounded_bad.v

@@ -13,4 +13,8 @@ module t (input clk);
   assert property (@(posedge clk) s_always a);
   assert property (@(posedge clk) s_always [2:$] a);
 
+  // A weak always range may only place $ on the high bound; an unbounded low
+  // bound is not a legal cycle_delay_const_range_expression.
+  assert property (@(posedge clk) always [$:5] a);
+
 endmodule