Fix internal error on "output x; reg x = y;"

Changes

@@ -35,6 +35,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix compile error on Ubuntu 8.10. [Christopher Boumenot]
 
+**** Fix internal error on "output x; reg x = y;".
+
 * Verilator 3.681 2008/11/12
 
 ***  Add SystemVerilog unique and priority case.

src/verilog.y

@@ -764,7 +764,7 @@ sigIdRange<varp>:
 regSigId<varp>:
 		yaID rangeListE				{ $$ = V3Parse::createVariable(CRELINE(), *$1, $2); }
 	|	yaID rangeListE '=' constExpr		{ $$ = V3Parse::createVariable(CRELINE(), *$1, $2);
-							  $$->addNext(new AstInitial($3,new AstAssign($3, new AstVarRef($3, $$, true), $4))); }
+							  $$->addNext(new AstInitial($3,new AstAssign($3, new AstVarRef($3, *$1, true), $4))); }
 	;
 
 sigId<varp>:	yaID					{ $$ = V3Parse::createVariable(CRELINE(), *$1, NULL); }

test_regress/driver.pl

@@ -430,7 +430,8 @@ sub compile {
 			      "make", "-f".getcwd()."/Makefile_obj",
 			      "VM_PREFIX=$self->{VM_PREFIX}",
 			      ($param{make_main}?"":"MAKE_MAIN=0"),
-			      "$self->{VM_PREFIX}",  # not default, as we don't need archive
+			      ($param{benchmark}?"OPT_FAST=-O2":""),
+			      "$self->{VM_PREFIX}",  # bypass default rule, as we don't need archive
 			      ($param{make_flags}||""),
 			      ]);
 	}

test_regress/t/t_EXAMPLE.v

@@ -54,6 +54,7 @@ module t (/*AUTOARG*/
       if (cyc==0) begin
 	 // Setup
 	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
       end
       else if (cyc<10) begin
 	 sum <= 64'h0;

test_regress/t/t_var_set_link.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_var_set_link.v

@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   state,
+   // Inputs
+   clk
+   );
+   input clk;
+
+   // Gave "Internal Error: V3Broken.cpp:: Broken link in node"
+   output [1:0] state;
+   reg [1:0] 	state = 2'b11;
+   always @ (posedge clk) begin
+      state <= state;
+   end
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule