mirror of
https://github.com/verilator/verilator.git
synced 2026-09-04 08:33:38 +02:00
+15
-6
@@ -900,8 +900,9 @@ public:
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const AstBasicDType* basicp() const { return m_basicp; }
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// Make a plan for variables after split
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// when skipUnused==true, split variable for unread bits will not be created.
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std::vector<SplitNewVar> splitPlan(bool skipUnused) const {
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std::vector<SplitNewVar> splitPlan(const AstVar* varp, bool skipUnused) const {
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UASSERT(m_dedupDone, "dedup() must be called before");
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AstNodeDType* const dtypep = varp->dtypeSkipRefp();
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std::vector<SplitNewVar> plan;
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std::vector<std::pair<int, bool>> points; // <bit location, is end>
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points.reserve(m_lhs.size() * 2 + 2); // 2 points will be added per one PackedVarRefEntry
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@@ -909,9 +910,17 @@ public:
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points.emplace_back(ref.lsb(), false); // Start of a region
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points.emplace_back(ref.msb() + 1, true); // End of a region
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}
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int bit_hi, bit_lo;
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if (basicp() == dtypep) {
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bit_hi = basicp()->hi();
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bit_lo = basicp()->lo();
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} else { // packed struct, packed array. lo is 0
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bit_hi = dtypep->width() - 1;
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bit_lo = 0;
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}
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if (skipUnused && !m_rhs.empty()) { // Range to be read must be kept, so add points here
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int lsb = m_basicp->hi() + 1;
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int msb = m_basicp->lo() - 1;
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int lsb = bit_hi + 1;
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int msb = bit_lo - 1;
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for (const PackedVarRefEntry& ref : m_rhs) {
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lsb = std::min(lsb, ref.lsb());
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msb = std::max(msb, ref.msb());
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@@ -921,8 +930,8 @@ public:
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points.emplace_back(msb + 1, true);
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}
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if (!skipUnused) { // All bits are necessary
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points.emplace_back(m_basicp->lo(), false);
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points.emplace_back(m_basicp->hi() + 1, true);
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points.emplace_back(bit_lo, false);
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points.emplace_back(bit_hi + 1, true);
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}
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std::sort(points.begin(), points.end(), SortByFirst());
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@@ -1154,7 +1163,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
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<< " which has " << ref.lhs().size() << " lhs refs and "
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<< ref.rhs().size() << " rhs refs will be split.\n");
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std::vector<SplitNewVar> vars
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= ref.splitPlan(!varp->isTrace()); // If traced, all bit must be kept
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= ref.splitPlan(varp, !varp->isTrace()); // If traced, all bit must be kept
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if (vars.empty()) continue;
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if (vars.size() == 1 && vars.front().bitwidth() == varp->width())
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continue; // No split
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