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Internals: Create VAccess class. No functional change intended.
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+2
-2
@@ -383,7 +383,7 @@ protected:
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SplitVarStdVertex* vstdp = reinterpret_cast<SplitVarStdVertex*>(vscp->user1p());
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// SPEEDUP: We add duplicate edges, that should be fixed
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if (m_inDly && nodep->lvalue()) {
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if (m_inDly && nodep->access().isWrite()) {
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UINFO(4, " VARREFDLY: " << nodep << endl);
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// Delayed variable is different from non-delayed variable
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if (!vscp->user2p()) {
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@@ -398,7 +398,7 @@ protected:
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new SplitLVEdge(&m_graph, vpostp, vxp);
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}
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} else { // Nondelayed assignment
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if (nodep->lvalue()) {
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if (nodep->access().isWrite()) {
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// Non-delay; need to maintain existing ordering
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// with all consumers of the signal
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UINFO(4, " VARREFLV: " << nodep << endl);
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