Commentary: Changes update

Changes

@@ -22,14 +22,18 @@ Verilator 5.051 devel
 * Add error when scalar is passed to array task argument (#7948). [Pawel Klopotek]
 * Add MULTIDRIVENPROC warning for signals driven by multiple plain always blocks (#7968). [Aisha]
 * Add FSM arc and state coverage to verilator_coverage .info output (#7972) (#7973). [Igor Zaworski, Antmicro Ltd.]
+* Support embedded covergroup member references (#7749) (#8015). [Marco Bartoli]
 * Support a sequence used as an event control (#7797) (#7846). [Yilou Wang]
 * Support `[\*N:$]` consecutive repetition (#7940). [Artur Bieniek, Antmicro Ltd.]
 * Support dynamic containers in unique constraints (#7947). [Adam Kostrzewski, Antmicro Ltd.]
 * Support delayed tristate gates (#7960) (#7961). [Patrick Creighton]
+* Support `default clocking` (#7984). [Kamil Danecki, Antmicro Ltd.]
+* Support `weak`/`strong` keywords in property expressions (#8054). [Artur Bieniek, Antmicro Ltd.]
 * Optimize random initialization. [Geza Lore, Testorrent USA, Inc.]
 * Optimize more always blocks in DFG (#7775). [Geza Lore, Testorrent USA, Inc.]
 * Optimize assertion NFAs using bit-vector ring buffers (#7885). [Artur Bieniek, Antmicro Ltd.]
 * Optimize VPI symbol registration and scope construction (#7936). [Nick Brereton]
+* Fix $finish continuing event loop (#7267) (#7950). [Artur Bieniek, Antmicro Ltd.]
 * Fix $display accepting streaming concat arguments (#7663) (#7890). [Jaeuk Lee]
 * Fix DFG misoptimizing bound checks (#7755). [Jakub Michalski]
 * Fix unique0 case side effects (#7787). [Pawel Klopotek]
@@ -37,6 +41,8 @@ Verilator 5.051 devel
 * Fix cleaning purity cache after assertions. [Geza Lore, Testorrent USA, Inc.]
 * Fix uncaught type error leading to invalid C++ output (#7814). [Geza Lore, Testorrent USA, Inc.]
 * Fix internal error for coverpoints that reference a covergroup formal parameter (#7853 partial) (#7889). [Matthew Ballance]
+* Fix immediate disable of fork join branches (#7856) (#7931). [Marco Bartoli]
+* Fix self-disable of named blocks with forks (Part of #7857) (#7996) (#8006). [Marco Bartoli]
 * Fix clang++ ambiguous overload of '==' operator (#7863). [Pawel Kojma, Antmicro Ltd.]
 * Fix heap-use-after-free in `VlRNG::VlRNG()` (#7865). [Dragon-Git]
 * Fix mixed-width inside and dist range bounds failing randomization (#7875). [Yilou Wang]
@@ -60,14 +66,41 @@ Verilator 5.051 devel
 * Fix unlinked error with function call in derived class parameter (#7923). [Mateusz Gancarz, Antmicro Ltd.]
 * Fix class parameter resolution (#7935).
 * Fix FSM detection of coverage-only branches (#7941) (#7942). [Patrick Creighton]
+* Fix use-after-free in V3LinkDotIfaceCapture (#7943). [Nick Brereton]
 * Fix sampled-value clocks in repeated assertions (#7944). [Artur Bieniek, Antmicro Ltd.]
+* Fix queued $finish/$stop request thread ordering (#7946 prep) (#7952). [Yilou Wang]
+* Fix DFG nested shifts with overflowing shift amount (#7955) (#7977).
+* Fix timing controls in interface tasks called via virtual interface (#7959). [Yilou Wang]
 * Fix lambda parameter types in queue min and max (#7962). [Bartosz Skorowski]
 * Fix solve-before dropping all soft constraints in randomize() (#7963). [Yilou Wang]
+* Fix generic interface param resolution in module/cell parameterization (#7970) (#7971). [David Garau]
 * Fix lost writes when select width exceeds variable width (#7975). [Bartosz Skorowski]
-* Fix variable scope in unique on dynamic array (#7981). [Kornel Uriasz, Antmicro Ltd.]
-* Fix table optimization causing not contextually convertible to bool error (#7983). [Jakub Michalski]
 * Fix $fgets being mis-optimized away (#7976). [G-A. Kamendje]
 * Fix SYNCASYNCNET false positive with changed non-edge logic (#7980). [Oron Port]
+* Fix variable scope in unique on dynamic array (#7981). [Kornel Uriasz, Antmicro Ltd.]
+* Fix table optimization causing not contextually convertible to bool error (#7983). [Jakub Michalski]
+* Fix wait fork trigger temporary split across generated functions (#7985) (#7986). [Marco Brambilla]
+* Fix randomize() with a user variable named 'item' (#7993) (#7994).
+* Fix UNSATCONSTR reporting constraint indices above 9 (#7995). [Yilou Wang]
+* Fix MULTIDRIVEN/PROC warning suppression via lint_off (#8000). [Gilberto Abram]
+* Fix force not substituted into an unpacked array index (#8002).
+* Fix dist weights ignored when an item is not a literal (#8003).
+* Fix error when forcing an array element read at a run-time index (#8004).
+* Fix missing verilator_coverage in cmake install (#8008) (#8011).
+* Fix dist inside a foreach nested in a constraint if (#8016).
+* Fix gcov dump on warnings discarding later coverage counts (#8017). [Yilou Wang]
+* Fix unique constraint crash, guards, and size (#8018).
+* Fix assignment pattern key constant expressions (#8029) (#8030). [Josep Sans]
+* Fix skipping optimization for unpacked data types (#8031). [Kornel Uriasz, Antmicro Ltd.]
+* Fix gate deduplication with function arguments (#8038). [JOTEGO]
+* Fix conditional expression with parameterized classes (#8039). [Pawel Klopotek, Antmicro Ltd.]
+* Fix array size references in constraints (#8040). [Kornel Uriasz, Antmicro Ltd.]
+* Fix mid-range consecutive repetition rejects (#8041). [Artur Bieniek, Antmicro Ltd.]
+* Fix write access to dynamic arrays (#8043). [Bartosz Skorowski, Antmicro Ltd.]
+* Fix nondeterminism in trace stage (#8046). [Sumanth Kadiyala]
+* Fix force helpers in multiply instantiated modules (#8047). [Artur Bieniek, Antmicro Ltd.]
+* Fix pin to non-existent port with PINNOTFOUND suppressed (#8051) (#8052). [Nikolai Kumar]
+* Fix wildcard equality against a 4-state constant in an assertion (#8056) (#8057). [Nikolai Kumar]
 
 
 Verilator 5.050 2026-07-01

docs/spelling.txt

@@ -709,6 +709,7 @@ de
 dearray
 deassign
 debugi
+deduplication
 defenv
 defname
 defparam
@@ -1177,6 +1178,7 @@ tcmalloc
 tcmalloc
 tenghtt
 testbench
+testbenches
 threadsafe
 threashold
 timeInc

test_regress/t/t_assert_sampled_const.v

@@ -10,7 +10,7 @@
 // verilog_format: on
 
 module t (
-  input logic clk
+    input logic clk
 );
 
   localparam OP_UNTYPED = 3'b000;

test_regress/t/t_clocking_default_bad.v

@@ -5,8 +5,8 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input clk
+    input clk
-  );
+);
 
   clocking cb1 @(posedge clk);
   endclocking

test_regress/t/t_clocking_default_bad2.v

@@ -5,10 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input clk
+    input clk
-  );
+);
 
-  initial begin: foo
+  initial begin : foo
   end
 
   default clocking cb_nonexistent;

test_regress/t/t_clocking_default_identifier.v

@@ -5,16 +5,16 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input clk
+    input clk
-  );
+);
   int cyc = 0;
 
   always @(negedge clk) begin  // negedge so there is nothing after $finish
-     cyc <= cyc + 1;
+    cyc <= cyc + 1;
-     if (cyc == 12) begin
+    if (cyc == 12) begin
-        $write("*-* All Finished *-*\n");
+      $write("*-* All Finished *-*\n");
-        $finish;
+      $finish;
-     end
+    end
   end
 
   clocking cb @(posedge clk);
@@ -22,11 +22,11 @@ module t (
 
   default clocking cb;
   initial begin
-    ## 2;
+    ##2;
     if ($time != 20) $stop;
-    ## 5;
+    ##5;
     if ($time != 70) $stop;
-    ## 3;
+    ##3;
     if ($time != 100) $stop;
   end
 endmodule

test_regress/t/t_constraint_arr_with_arrsize_unsup.v

@@ -17,7 +17,7 @@ class Indep;
   Sub s[];
 
   function new();
-    s = new [10];
+    s = new[10];
   endfunction
 endclass
 

test_regress/t/t_constraint_dyn_size_class.v

@@ -4,25 +4,25 @@
 // SPDX-FileCopyrightText: 2026 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
-/*verilator lint_off*/
+// verilator lint_off
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
+`define check_range(gotv, minv, maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
-/*verilator lint_on*/
+// verilog_format: on
+// verilator lint_on
 
 class SubSubClass;
   rand int subVal;
   rand int subArr[];
 
-  constraint c{
+  constraint c {subArr.size < 10;}
-    subArr.size < 10;
-  }
 endclass
 
 class SubClass;
   rand int subVal;
   rand int subArr[];
-  rand int assocArr[string] = '{ "test": 1, "test2" : 2 };
+  rand int assocArr[string] = '{"test": 1, "test2" : 2};
   SubSubClass ssc;
 
   function new();
@@ -48,7 +48,8 @@ class BaseClass;
   constraint bc {
     arr.size < 10;
     arr.size > 5;
-  };
+  }
+  ;
 endclass
 
 class ExtClass0 extends BaseClass;
@@ -56,24 +57,18 @@ class ExtClass0 extends BaseClass;
     return (cls.randomize() with {
       // If with arr.size on array, that's a field of class
       // calling randomize() with
-      if (arr.size > 0) {
+      if (arr.size > 0) {val0 inside {arr};}
-        val0 inside {arr};
-      }
 
       // If with arr.size on array thats a field inside subclass
       // chain
-      if (cls.sc.ssc.subArr.size > 0 ) {
+      if (cls.sc.ssc.subArr.size > 0) {val1 == 'hDEADBEEF;}
-        val1 == 'hDEADBEEF;
-      }
 
       // Randomizable array size
       sc.subArr.size > 25;
       sc.subArr.size < 50;
 
       // If with associative array size
-      if (sc.assocArr.size > 0) {
+      if (sc.assocArr.size > 0) {val2 == 'hCAFEBABE;}
-        val2 == 'hCAFEBABE;
-      }
     });
   endfunction
 endclass
@@ -81,10 +76,8 @@ endclass
 class ExtClass1 extends BaseClass;
   // Class that extends BaseClass and uses arr.size variable
   constraint c {
-    unique{arr};
+    unique {arr};
-    foreach(arr[i]) {
+    foreach (arr[i]) {arr[i] != 0;}
-      arr[i] != 0;
-    }
   }
 endclass
 
@@ -97,7 +90,7 @@ module t;
     indep = new;
     ext0 = new;
     ext1 = new;
-    repeat(10) begin
+    repeat (10) begin
       `checkh(ext0.randomize(), 1);
       `checkh(ext0.randomize(), 1);
       `checkh(ext0.randomize_gpr(indep), 1);
@@ -122,7 +115,7 @@ module t;
       end
     end
 
-  $write("*-* All Finished *-*\n");
+    $write("*-* All Finished *-*\n");
-  $finish();
+    $finish();
   end
 endmodule

test_regress/t/t_disable_fork_instances.v

@@ -28,11 +28,11 @@ class QueueHolder;
   endtask
 endclass
 
-module child(
+module child (
-  input bit do_disable,
+    input bit do_disable,
-  output bit survived_a,
+    output bit survived_a,
-  output bit survived_b,
+    output bit survived_b,
-  output bit done
+    output bit done
 );
 
   initial begin
@@ -42,7 +42,8 @@ module child(
           #1;
           disable fork_blk;
           $stop;
-        end else begin
+        end
+        else begin
           #6;
           survived_a = 1'b1;
         end
@@ -50,7 +51,8 @@ module child(
       begin
         if (do_disable) begin
           #5 $stop;
-        end else begin
+        end
+        else begin
           #6;
           survived_b = 1'b1;
         end
@@ -72,18 +74,18 @@ module t;
   bit done1;
   QueueHolder holder;
 
-  child child0(
+  child child0 (
-    .do_disable(do_disable0),
+      .do_disable(do_disable0),
-    .survived_a(survived_a0),
+      .survived_a(survived_a0),
-    .survived_b(survived_b0),
+      .survived_b(survived_b0),
-    .done(done0)
+      .done(done0)
   );
 
-  child child1(
+  child child1 (
-    .do_disable(do_disable1),
+      .do_disable(do_disable1),
-    .survived_a(survived_a1),
+      .survived_a(survived_a1),
-    .survived_b(survived_b1),
+      .survived_b(survived_b1),
-    .done(done1)
+      .done(done1)
   );
 
   initial begin

test_regress/t/t_dynarray_select.v

@@ -24,7 +24,7 @@ module t;
     gen = new;
     arr = new[1];
     arr[0][gen.get_num(3)] = 1'b1;
-    `checkh(arr[0][3],1'b1);
+    `checkh(arr[0][3], 1'b1);
     $finish;
   end
 endmodule

test_regress/t/t_gate_dedupe_func.v

@@ -4,7 +4,7 @@
 // SPDX-FileCopyrightText: 2026 Jose Tejada
 // SPDX-License-Identifier: CC0-1.0
 
-module jtcop_bac06(
+module jtcop_bac06 (
     input rst,
     input clk,
     input [15:0] cpu_dout,
@@ -31,29 +31,40 @@ module jtcop_bac06(
   end
 
   function [15:0] combine(input [15:0] din);
-    combine = {cpu_dsn[1] ? din[15:8] : cpu_dout[15:8],
+    combine = {cpu_dsn[1] ? din[15:8] : cpu_dout[15:8], cpu_dsn[0] ? din[7:0] : cpu_dout[7:0]};
-               cpu_dsn[0] ? din[7:0] : cpu_dout[7:0]};
   endfunction
 
   always @(posedge clk) begin
     if (rst) vscr <= {def_cfg[7], def_cfg[6]};
-    else case (cpu_addr[2:1])
+    else
-      0: hscr <= combine(hscr);
+      case (cpu_addr[2:1])
-      1: vscr <= combine(vscr);
+        0: hscr <= combine(hscr);
-      2: colscr_sh <= cpu_dout[3:0];
+        1: vscr <= combine(vscr);
-      3: rowscr_sh <= cpu_dout[3:0];
+        2: colscr_sh <= cpu_dout[3:0];
-    endcase
+        3: rowscr_sh <= cpu_dout[3:0];
+      endcase
   end
 endmodule
 
-module jtcop_game(input clk, output [7:0] st_dout);
+module jtcop_game (
+    input clk,
+    output [7:0] st_dout
+);
   wire [12:1] cpu_addr;
-  jtcop_main u_main(.cpu_addr(cpu_addr));
+  jtcop_main u_main (.cpu_addr(cpu_addr));
-  jtcop_bac06 u_ba2(.rst(rst), .clk(clk), .cpu_dout(ba2_din),
+  jtcop_bac06 u_ba2 (
-                    .cpu_addr(cpu_addr), .cpu_dsn(ba2_dsn), .st_addr(st_addr),
+      .rst(rst),
-                    .st_dout(st_dout));
+      .clk(clk),
+      .cpu_dout(ba2_din),
+      .cpu_addr(cpu_addr),
+      .cpu_dsn(ba2_dsn),
+      .st_addr(st_addr),
+      .st_dout(st_dout)
+  );
 endmodule
 
-module jtcop_main(output [12:1] cpu_addr);
+module jtcop_main (
+    output [12:1] cpu_addr
+);
   assign cpu_addr = '0;
 endmodule

test_regress/t/t_iface_typedef_capture_uaf.v

@@ -42,7 +42,10 @@ module t;
   for (genvar g = 0; g < 2; ++g) begin : gen_block
     avmm_if #(.DW(32 * (g + 1))) m_if ();
     avmm_if #(.DW(32 * (g + 1))) s_if ();
-    avmm_autopipeline pipe (.master(m_if), .slave(s_if));
+    avmm_autopipeline pipe (
+        .master(m_if),
+        .slave(s_if)
+    );
   end
 
   initial begin

test_regress/t/t_lint_pinnotfound_deparam.v

@@ -10,7 +10,5 @@ module child ();
 endmodule
 
 module t;
-  child u_child (
+  child u_child (.missing_port(1'b0));
-    .missing_port (1'b0)
-  );
 endmodule

test_regress/t/t_opt_unpacked.v

@@ -8,7 +8,7 @@
 // expression when trying to optimise bit operations.
 module t;
   class Cls;
-  endclass;
+  endclass
 
   class subCls;
     bit val = 1'b1;
@@ -20,7 +20,7 @@ module t;
         $stop();
       end
     endfunction
-  endclass;
+  endclass
 
   subCls sc;
 

test_regress/t/t_param_class_cond.v

@@ -10,14 +10,18 @@ endclass
 
 typedef Base Base_t;
 
-class SubA #(type T = int) extends Base_t;
+class SubA #(
+    type T = int
+) extends Base_t;
 endclass
 
-class SubB #(type T = int) extends Base_t;
+class SubB #(
+    type T = int
+) extends Base_t;
 endclass
 
-typedef SubA #(int) SubAInt_t;
+typedef SubA#(int) SubAInt_t;
-typedef SubB #(int) SubBInt_t;
+typedef SubB#(int) SubBInt_t;
 
 class Container;
   local SubAInt_t a;

test_regress/t/t_prop_bad.out

@@ -1,47 +1,47 @@
-%Error: t/t_prop_bad.v:14:40: syntax error, unexpected s_eventually, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:14:41: syntax error, unexpected s_eventually, expecting IDENTIFIER-for-type
-   14 |   assert property (@(posedge clk) weak(s_eventually a));
+   14 |   assert property (@(posedge clk) weak (s_eventually a));
-      |                                        ^~~~~~~~~~~~
+      |                                         ^~~~~~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_prop_bad.v:15:40: syntax error, unexpected s_always, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:15:41: syntax error, unexpected s_always, expecting IDENTIFIER-for-type
-   15 |   assert property (@(posedge clk) weak(s_always [1:2] a));
+   15 |   assert property (@(posedge clk) weak (s_always[1: 2] a));
-      |                                        ^~~~~~~~
+      |                                         ^~~~~~~~
-%Error: t/t_prop_bad.v:16:40: syntax error, unexpected nexttime, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:16:41: syntax error, unexpected nexttime, expecting IDENTIFIER-for-type
-   16 |   assert property (@(posedge clk) weak(nexttime a));
+   16 |   assert property (@(posedge clk) weak (nexttime a));
-      |                                        ^~~~~~~~
+      |                                         ^~~~~~~~
-%Error: t/t_prop_bad.v:17:40: syntax error, unexpected s_nexttime, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:17:41: syntax error, unexpected s_nexttime, expecting IDENTIFIER-for-type
-   17 |   assert property (@(posedge clk) weak(s_nexttime a));
+   17 |   assert property (@(posedge clk) weak (s_nexttime a));
-      |                                        ^~~~~~~~~~
+      |                                         ^~~~~~~~~~
-%Error: t/t_prop_bad.v:18:40: syntax error, unexpected always, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:18:41: syntax error, unexpected always, expecting IDENTIFIER-for-type
-   18 |   assert property (@(posedge clk) weak(always a));
+   18 |   assert property (@(posedge clk) weak (always a));
-      |                                        ^~~~~~
+      |                                         ^~~~~~
-%Error: t/t_prop_bad.v:19:40: syntax error, unexpected eventually, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:19:41: syntax error, unexpected eventually, expecting IDENTIFIER-for-type
-   19 |   assert property (@(posedge clk) weak(eventually [1:2] a));
+   19 |   assert property (@(posedge clk) weak (eventually[1: 2] a));
-      |                                        ^~~~~~~~~~
+      |                                         ^~~~~~~~~~
-%Error: t/t_prop_bad.v:20:42: syntax error, unexpected |->
+%Error: t/t_prop_bad.v:20:43: syntax error, unexpected |->
-   20 |   assert property (@(posedge clk) weak(a |-> b));
+   20 |   assert property (@(posedge clk) weak (a |-> b));
-      |                                          ^~~
+      |                                           ^~~
-%Error: t/t_prop_bad.v:21:42: syntax error, unexpected |=>
+%Error: t/t_prop_bad.v:21:43: syntax error, unexpected |=>
-   21 |   assert property (@(posedge clk) weak(a |=> b));
+   21 |   assert property (@(posedge clk) weak (a |=> b));
-      |                                          ^~~
+      |                                           ^~~
-%Error: t/t_prop_bad.v:22:42: syntax error, unexpected implies
+%Error: t/t_prop_bad.v:22:43: syntax error, unexpected implies
-   22 |   assert property (@(posedge clk) weak(a implies b));
+   22 |   assert property (@(posedge clk) weak (a implies b));
-      |                                          ^~~~~~~
+      |                                           ^~~~~~~
-%Error: t/t_prop_bad.v:23:42: syntax error, unexpected iff
+%Error: t/t_prop_bad.v:23:43: syntax error, unexpected iff
-   23 |   assert property (@(posedge clk) weak(a iff b));
+   23 |   assert property (@(posedge clk) weak (a iff b));
-      |                                          ^~~
+      |                                           ^~~
-%Error: t/t_prop_bad.v:24:40: syntax error, unexpected accept_on, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:24:41: syntax error, unexpected accept_on, expecting IDENTIFIER-for-type
-   24 |   assert property (@(posedge clk) weak(accept_on (a) b));
+   24 |   assert property (@(posedge clk) weak (accept_on (a) b));
-      |                                        ^~~~~~~~~
+      |                                         ^~~~~~~~~
-%Error: t/t_prop_bad.v:25:40: syntax error, unexpected reject_on, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:25:41: syntax error, unexpected reject_on, expecting IDENTIFIER-for-type
-   25 |   assert property (@(posedge clk) weak(reject_on (a) b));
+   25 |   assert property (@(posedge clk) weak (reject_on (a) b));
-      |                                        ^~~~~~~~~
+      |                                         ^~~~~~~~~
 %Error: t/t_prop_bad.v:26:40: syntax error, unexpected if, expecting IDENTIFIER-for-type
    26 |   assert property (@(posedge clk) weak(if (a) b else c));
       |                                        ^~
-%Error: t/t_prop_bad.v:27:40: syntax error, unexpected strong, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:27:41: syntax error, unexpected strong, expecting IDENTIFIER-for-type
-   27 |   assert property (@(posedge clk) weak(strong(a)));
+   27 |   assert property (@(posedge clk) weak (strong (a)));
-      |                                        ^~~~~~
+      |                                         ^~~~~~
-%Error: t/t_prop_bad.v:28:42: syntax error, unexpected weak, expecting IDENTIFIER-for-type
+%Error: t/t_prop_bad.v:28:43: syntax error, unexpected weak, expecting IDENTIFIER-for-type
-   28 |   assert property (@(posedge clk) strong(weak(a)));
+   28 |   assert property (@(posedge clk) strong (weak (a)));
-      |                                          ^~~~
+      |                                           ^~~~
 %Error: Exiting due to

test_regress/t/t_prop_bad.v

@@ -11,19 +11,19 @@ module t (
   logic b = 1'b1;
   logic c = 1'b1;
 
-  assert property (@(posedge clk) weak(s_eventually a));
+  assert property (@(posedge clk) weak (s_eventually a));
-  assert property (@(posedge clk) weak(s_always [1:2] a));
+  assert property (@(posedge clk) weak (s_always[1: 2] a));
-  assert property (@(posedge clk) weak(nexttime a));
+  assert property (@(posedge clk) weak (nexttime a));
-  assert property (@(posedge clk) weak(s_nexttime a));
+  assert property (@(posedge clk) weak (s_nexttime a));
-  assert property (@(posedge clk) weak(always a));
+  assert property (@(posedge clk) weak (always a));
-  assert property (@(posedge clk) weak(eventually [1:2] a));
+  assert property (@(posedge clk) weak (eventually[1: 2] a));
-  assert property (@(posedge clk) weak(a |-> b));
+  assert property (@(posedge clk) weak (a |-> b));
-  assert property (@(posedge clk) weak(a |=> b));
+  assert property (@(posedge clk) weak (a |=> b));
-  assert property (@(posedge clk) weak(a implies b));
+  assert property (@(posedge clk) weak (a implies b));
-  assert property (@(posedge clk) weak(a iff b));
+  assert property (@(posedge clk) weak (a iff b));
-  assert property (@(posedge clk) weak(accept_on (a) b));
+  assert property (@(posedge clk) weak (accept_on (a) b));
-  assert property (@(posedge clk) weak(reject_on (a) b));
+  assert property (@(posedge clk) weak (reject_on (a) b));
   assert property (@(posedge clk) weak(if (a) b else c));
-  assert property (@(posedge clk) weak(strong(a)));
+  assert property (@(posedge clk) weak (strong (a)));
-  assert property (@(posedge clk) strong(weak(a)));
+  assert property (@(posedge clk) strong (weak (a)));
 endmodule

test_regress/t/t_prop_strong_unsup.out

@@ -1,6 +1,6 @@
 %Error-UNSUPPORTED: t/t_prop_strong_unsup.v:12:20: Unsupported: strong property in assume.
                                                  : ... note: In instance 't'
-   12 |   assume property (@(posedge clk) strong(a ##1 a));
+   12 |   assume property (@(posedge clk) strong (a ##1 a));
       |                    ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_prop_strong_unsup.v

@@ -9,5 +9,5 @@ module t (
 );
   logic a = 1'b1;
 
-  assume property (@(posedge clk) strong(a ##1 a));
+  assume property (@(posedge clk) strong (a ##1 a));
 endmodule

test_regress/t/t_prop_strong_unused.v

@@ -10,6 +10,6 @@ module t (
   logic a = 1'b1;
 
   property p_unused_strong;
-    @(posedge clk) strong(a);
+    @(posedge clk) strong (a);
   endproperty
 endmodule

test_regress/t/t_prop_weak.v

@@ -21,37 +21,42 @@ module t (
     ++cyc;
     if (cyc < 5) begin
       ->e;
-    end else begin
+    end
+    else begin
       `checkd(hit, 'b1111111);
       $write("*-* All Finished *-*\n");
       $finish;
     end
   end
 
-  assert property (@(e) weak(##1 1 ##1 1));
+  assert property (@(e) weak (##1 1 ##1 1));
-  assert property (@(e) weak(1 ##1 1 ##1 1));
+  assert property (@(e) weak (1 ##1 1 ##1 1));
-  assert property (@(e) weak(1 ##1 1));
+  assert property (@(e) weak (1 ##1 1));
 
-  assert property (@(e) weak(##1 1 ##1 1)) begin
+  assert property (@(e) weak (##1 1 ##1 1)) begin
     hit |= 'b1;
   end
-  assert property (@(e) weak(1 ##1 1 ##1 1)) begin
+  assert property (@(e) weak (1 ##1 1 ##1 1)) begin
     hit |= 'b10;
   end
-  assert property (@(e) weak(1 ##1 1)) begin
+  assert property (@(e) weak (1 ##1 1)) begin
     hit |= 'b100;
   end
 
-  assert property (@(e) weak(##1 1 ##1 0)) else begin
+  assert property (@(e) weak (##1 1 ##1 0))
+  else begin
     hit |= 'b1000;
   end
-  assert property (@(e) weak(##1 0)) else begin
+  assert property (@(e) weak (##1 0))
+  else begin
     hit |= 'b10000;
   end
-  assert property (@(e) weak(1 ##1 1 ##1 0)) else begin
+  assert property (@(e) weak (1 ##1 1 ##1 0))
+  else begin
     hit |= 'b100000;
   end
-  assert property (@(e) weak(1 ##1 0)) else begin
+  assert property (@(e) weak (1 ##1 0))
+  else begin
     hit |= 'b1000000;
   end
 

test_regress/t/t_timing_wait_fork_split.v

@@ -11,23 +11,34 @@
 
 module t;
   logic clk = 1'b0;
-  int   cnt = 0;
+  int cnt = 0;
 
   always #5 clk = ~clk;
 
   task automatic phase(int n);
-    fork begin @(posedge clk); cnt += n; end join_none
+    fork
+      begin
+        @(posedge clk);
+        cnt += n;
+      end
+    join_none
     wait fork;
   endtask
 
   initial begin
-    fork @(posedge clk); join_none
+    fork
+      @(posedge clk);
+    join_none
     wait fork;
     phase(1);
-    fork @(negedge clk); join_none
+    fork
+      @(negedge clk);
+    join_none
     wait fork;
     phase(2);
-    fork @(posedge clk); join_none
+    fork
+      @(posedge clk);
+    join_none
     wait fork;
     phase(4);
     if (cnt != 7) begin