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Support sequence intersect operator (#7374)
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+2
-1
@@ -294,8 +294,9 @@ class WidthVisitor final : public VNVisitor {
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// Widths: 1 bit out, lhs 1 bit, rhs 1 bit; Real: converts via compare with 0
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void visit(AstLogAnd* nodep) override { visit_log_and_or(nodep); }
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void visit(AstLogOr* nodep) override { visit_log_and_or(nodep); }
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// Sequence and/or (IEEE 1800-2023 16.9.2), same width rules as LogAnd/LogOr
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// Sequence and/or/intersect (IEEE 1800-2023 16.9.2), same width rules as LogAnd/LogOr
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void visit(AstSAnd* nodep) override { visit_log_and_or(nodep); }
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void visit(AstSIntersect* nodep) override { visit_log_and_or(nodep); }
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void visit(AstSOr* nodep) override { visit_log_and_or(nodep); }
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void visit(AstLogEq* nodep) override {
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// Conversion from real not in IEEE, but a fallout
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