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Remove tabs from --xml output.

This commit is contained in:
Wilson Snyder 2017-11-13 18:24:18 -05:00
parent 562f17ea4b
commit 12607abb33
5 changed files with 41 additions and 41 deletions
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2
include/verilated.cpp
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@ -726,7 +726,7 @@ static inline void _vl_vsss_read(FILE* fp, int& floc, WDataInP fromp, const std:
_vl_vsss_advance(fp, floc); _vl_vsss_advance(fp, floc);
} }
*cp++ = '\0'; *cp++ = '\0';
//VL_DBG_MSGF("\t_read got='"<<tmpp<<"'\n"); //VL_DBG_MSGF(" _read got='"<<tmpp<<"'\n");
} }
static inline void _vl_vsss_setbit(WDataOutP owp, int obits, int lsb, int nbits, IData ld) VL_MT_SAFE { static inline void _vl_vsss_setbit(WDataOutP owp, int obits, int lsb, int nbits, IData ld) VL_MT_SAFE {
for (; nbits && lsb<obits; nbits--, lsb++, ld>>=1) { for (; nbits && lsb<obits; nbits--, lsb++, ld>>=1) {

4
src/V3EmitC.cpp
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@ -1003,7 +1003,7 @@ void EmitCStmts::emitVarDecl(AstVar* nodep, const string& prefixIfImp) {
if (nodep->isSc()) { if (nodep->isSc()) {
m_ctorVarsVec.push_back(nodep); m_ctorVarsVec.push_back(nodep);
if (nodep->attrScClocked() && nodep->isInput()) { if (nodep->attrScClocked() && nodep->isInput()) {
puts("sc_in_clk\t"); puts("sc_in_clk ");
} else { } else {
if (nodep->isInout()) puts("sc_inout<"); if (nodep->isInout()) puts("sc_inout<");
else if (nodep->isInput()) puts("sc_in<"); else if (nodep->isInput()) puts("sc_in<");
@ -1011,7 +1011,7 @@ void EmitCStmts::emitVarDecl(AstVar* nodep, const string& prefixIfImp) {
else nodep->v3fatalSrc("Unknown type"); else nodep->v3fatalSrc("Unknown type");
puts(nodep->scType()); puts(nodep->scType());
puts(">\t"); puts("> ");
} }
puts(nodep->name()); puts(nodep->name());
emitDeclArrayBrackets(nodep); emitDeclArrayBrackets(nodep);

2
src/V3File.cpp
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@ -591,7 +591,7 @@ const char* V3OutFormatter::indentStr(int num) {
static char str[MAXSPACE+20]; static char str[MAXSPACE+20];
char* cp = str; char* cp = str;
if (num>MAXSPACE) num=MAXSPACE; if (num>MAXSPACE) num=MAXSPACE;
if (m_lang!=LA_VERILOG) { // verilogPrefixedTree doesn't want tabs if (m_lang!=LA_VERILOG && m_lang!=LA_XML) { // verilogPrefixedTree doesn't want tabs
while (num>=8) { while (num>=8) {
*cp++ = '\t'; *cp++ = '\t';
num -= 8; num -= 8;

58
test_regress/t/t_xml_first.out
View File

@ -15,26 +15,26 @@
<var fl="e14" name="q" dtype_id="2"/> <var fl="e14" name="q" dtype_id="2"/>
<var fl="e16" name="between" dtype_id="2"/> <var fl="e16" name="between" dtype_id="2"/>
<instance fl="e18" name="cell1" defName="mod1"> <instance fl="e18" name="cell1" defName="mod1">
<port fl="e18" name="q" direction="out" portIndex="1"> <port fl="e18" name="q" direction="out" portIndex="1">
<varref fl="e18" name="between" dtype_id="2"/> <varref fl="e18" name="between" dtype_id="2"/>
</port> </port>
<port fl="e21" name="clk" direction="in" portIndex="2"> <port fl="e21" name="clk" direction="in" portIndex="2">
<varref fl="e21" name="clk" dtype_id="1"/> <varref fl="e21" name="clk" dtype_id="1"/>
</port> </port>
<port fl="e22" name="d" direction="in" portIndex="3"> <port fl="e22" name="d" direction="in" portIndex="3">
<varref fl="e22" name="d" dtype_id="2"/> <varref fl="e22" name="d" dtype_id="2"/>
</port> </port>
</instance> </instance>
<instance fl="e24" name="cell2" defName="mod2"> <instance fl="e24" name="cell2" defName="mod2">
<port fl="e24" name="d" direction="in" portIndex="1"> <port fl="e24" name="d" direction="in" portIndex="1">
<varref fl="e24" name="between" dtype_id="2"/> <varref fl="e24" name="between" dtype_id="2"/>
</port> </port>
<port fl="e27" name="q" direction="out" portIndex="2"> <port fl="e27" name="q" direction="out" portIndex="2">
<varref fl="e27" name="q" dtype_id="2"/> <varref fl="e27" name="q" dtype_id="2"/>
</port> </port>
<port fl="e29" name="clk" direction="in" portIndex="3"> <port fl="e29" name="clk" direction="in" portIndex="3">
<varref fl="e29" name="clk" dtype_id="1"/> <varref fl="e29" name="clk" dtype_id="1"/>
</port> </port>
</instance> </instance>
</module> </module>
<module fl="e33" name="mod1"> <module fl="e33" name="mod1">
@ -42,15 +42,15 @@
<var fl="e36" name="d" dtype_id="2"/> <var fl="e36" name="d" dtype_id="2"/>
<var fl="e37" name="q" dtype_id="2"/> <var fl="e37" name="q" dtype_id="2"/>
<always fl="e39"> <always fl="e39">
<sentree fl="e39"> <sentree fl="e39">
<senitem fl="e39"> <senitem fl="e39">
<varref fl="e39" name="clk" dtype_id="1"/> <varref fl="e39" name="clk" dtype_id="1"/>
</senitem> </senitem>
</sentree> </sentree>
<assigndly fl="e40" dtype_id="2"> <assigndly fl="e40" dtype_id="2">
<varref fl="e40" name="d" dtype_id="2"/> <varref fl="e40" name="d" dtype_id="2"/>
<varref fl="e40" name="q" dtype_id="2"/> <varref fl="e40" name="q" dtype_id="2"/>
</assigndly> </assigndly>
</always> </always>
</module> </module>
<module fl="e44" name="mod2"> <module fl="e44" name="mod2">
@ -58,8 +58,8 @@
<var fl="e47" name="d" dtype_id="2"/> <var fl="e47" name="d" dtype_id="2"/>
<var fl="e48" name="q" dtype_id="2"/> <var fl="e48" name="q" dtype_id="2"/>
<contassign fl="e51" dtype_id="2"> <contassign fl="e51" dtype_id="2">
<varref fl="e51" name="d" dtype_id="2"/> <varref fl="e51" name="d" dtype_id="2"/>
<varref fl="e51" name="q" dtype_id="2"/> <varref fl="e51" name="q" dtype_id="2"/>
</contassign> </contassign>
</module> </module>
<typetable fl="a0"> <typetable fl="a0">

16
test_regress/t/t_xml_tag.out
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@ -20,20 +20,20 @@
<basicdtype fl="e23" id="4" name="logic" left="31" right="0"/> <basicdtype fl="e23" id="4" name="logic" left="31" right="0"/>
<basicdtype fl="e8" id="1" name="logic"/> <basicdtype fl="e8" id="1" name="logic"/>
<structdtype fl="e14" id="2"> <structdtype fl="e14" id="2">
<memberdtype fl="e15" id="5" name="clk" tag="this is clk" sub_dtype_id="6"/> <memberdtype fl="e15" id="5" name="clk" tag="this is clk" sub_dtype_id="6"/>
<memberdtype fl="e16" id="7" name="k" sub_dtype_id="8"/> <memberdtype fl="e16" id="7" name="k" sub_dtype_id="8"/>
<memberdtype fl="e17" id="9" name="enable" tag="enable" sub_dtype_id="10"/> <memberdtype fl="e17" id="9" name="enable" tag="enable" sub_dtype_id="10"/>
<memberdtype fl="e18" id="11" name="data" tag="data" sub_dtype_id="12"/> <memberdtype fl="e18" id="11" name="data" tag="data" sub_dtype_id="12"/>
</structdtype> </structdtype>
<basicdtype fl="e15" id="6" name="logic"/> <basicdtype fl="e15" id="6" name="logic"/>
<basicdtype fl="e16" id="8" name="logic"/> <basicdtype fl="e16" id="8" name="logic"/>
<basicdtype fl="e17" id="10" name="logic"/> <basicdtype fl="e17" id="10" name="logic"/>
<basicdtype fl="e18" id="12" name="logic"/> <basicdtype fl="e18" id="12" name="logic"/>
<unpackarraydtype fl="e23" id="3" sub_dtype_id="2"> <unpackarraydtype fl="e23" id="3" sub_dtype_id="2">
<range fl="e23"> <range fl="e23">
<const fl="e23" name="32'h1" dtype_id="4"/> <const fl="e23" name="32'h1" dtype_id="4"/>
<const fl="e23" name="32'h0" dtype_id="4"/> <const fl="e23" name="32'h0" dtype_id="4"/>
</range> </range>
</unpackarraydtype> </unpackarraydtype>
<refdtype fl="e23" id="13" name="my_struct" sub_dtype_id="2"/> <refdtype fl="e23" id="13" name="my_struct" sub_dtype_id="2"/>
</typetable> </typetable>