Support pre/post increment/decrement inside && and || (#7683)
This commit is contained in:
Nick Brereton
GitHub
parent
9455dddab4
commit
125bdb45f5
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@ -54,12 +54,17 @@ VL_DEFINE_DEBUG_FUNCTIONS;
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//######################################################################
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class LinkIncVisitor final : public VNVisitor {
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// NODE STATE
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// AstLogAnd/AstLogOr::user1() -> bool. True if already lowered
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const VNUser1InUse m_inuser1;
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// STATE
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AstNodeFTask* m_ftaskp = nullptr; // Function or task we're inside
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AstNodeModule* m_modp = nullptr; // Module we're inside
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int m_modCompoundAssignmentsNum = 0; // Var name counter
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AstNode* m_insStmtp = nullptr; // Where to insert statement
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bool m_unsupportedHere = false; // Used to detect where it's not supported yet
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bool m_condEvalContext = false; // ++/-- is in a conditionally-evaluated position
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AstNodeExpr* m_incCondp = nullptr; // Gating condition for ++/-- in short-circuit context
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// METHODS
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void insertOnTop(AstNode* newp) {
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@ -144,8 +149,8 @@ class LinkIncVisitor final : public VNVisitor {
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}
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void visit(AstCaseItem* nodep) override {
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{
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VL_RESTORER(m_unsupportedHere);
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m_unsupportedHere = true;
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VL_RESTORER(m_condEvalContext);
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m_condEvalContext = true;
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iterateAndNextNull(nodep->condsp());
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}
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m_insStmtp = nullptr; // Next thing should be new statement
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@ -195,13 +200,64 @@ class LinkIncVisitor final : public VNVisitor {
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m_insStmtp = nullptr; // Next thing should be new statement
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}
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void unsupported_visit(AstNode* nodep) {
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VL_RESTORER(m_unsupportedHere);
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m_unsupportedHere = true;
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VL_RESTORER(m_condEvalContext);
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VL_RESTORER(m_incCondp);
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m_condEvalContext = true;
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// Not rescuable by short-circuit gating; drop the gate so nested ++/-- errors
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m_incCondp = nullptr;
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UINFO(9, "Marking unsupported " << nodep);
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iterateChildren(nodep);
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}
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void visit(AstLogAnd* nodep) override { unsupported_visit(nodep); }
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void visit(AstLogOr* nodep) override { unsupported_visit(nodep); }
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// Hoist LHS into a BLOCKTEMP so it is evaluated exactly once; otherwise the
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// gated RHS ++/-- could modify a variable the LHS reads.
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AstNodeExpr* captureLogicalLhsToTemp(AstNodeBiop* const nodep) {
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FileLine* const fl = nodep->fileline();
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AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
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const string name = "__VincGate"s + cvtToStr(++m_modCompoundAssignmentsNum);
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AstVar* const varp = new AstVar{
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fl, VVarType::BLOCKTEMP, name, VFlagChildDType{},
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new AstRefDType{fl, AstRefDType::FlagTypeOfExpr{}, lhsp->cloneTree(true)}};
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varp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
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if (m_ftaskp) varp->funcLocal(true);
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insertOnTop(varp);
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AstNode* tempInitp = new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, lhsp};
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// Gate by the enclosing condition so a side-effecting LHS isn't run on short-circuit
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if (m_incCondp) {
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tempInitp = new AstIf{fl, m_incCondp->cloneTreePure(true), tempInitp, nullptr};
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}
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insertBeforeStmt(nodep, tempInitp);
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nodep->lhsp(new AstVarRef{fl, varp, VAccess::READ});
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return new AstVarRef{fl, varp, VAccess::READ};
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}
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void handleShortCircuit(AstNodeBiop* const nodep, bool isOr) {
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// insertBeforeStmt retargets the parent iterator; skip on re-visit
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if (nodep->user1SetOnce()) return;
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VL_RESTORER(m_condEvalContext);
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VL_RESTORER(m_incCondp);
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iterateAndNextNull(nodep->lhsp());
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m_condEvalContext = true;
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AstNodeExpr* ownedCondp = nullptr;
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// Gate the RHS by the LHS condition if it evaluates any ++/-- anywhere within
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if (nodep->rhsp()->exists([](const AstNode* np) {
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return VN_IS(np, PreInc) || VN_IS(np, PreDec) || VN_IS(np, PostInc)
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|| VN_IS(np, PostDec) || VN_IS(np, AssignCompound);
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})) {
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// Const LHS or no statement context: clone-and-evaluate-twice is safe
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AstNodeExpr* lhsRefp = (!m_insStmtp || VN_IS(nodep->lhsp(), Const))
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? nodep->lhsp()->cloneTreePure(true)
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: captureLogicalLhsToTemp(nodep);
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// For ||, RHS runs when LHS is false; gate by !LHS
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if (isOr) lhsRefp = new AstLogNot{nodep->fileline(), lhsRefp};
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ownedCondp = m_incCondp ? new AstLogAnd{nodep->fileline(),
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m_incCondp->cloneTreePure(true), lhsRefp}
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: lhsRefp;
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m_incCondp = ownedCondp;
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}
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iterateAndNextNull(nodep->rhsp());
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if (ownedCondp) VL_DO_DANGLING(ownedCondp->deleteTree(), ownedCondp);
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}
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void visit(AstLogAnd* nodep) override { handleShortCircuit(nodep, /*isOr=*/false); }
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void visit(AstLogOr* nodep) override { handleShortCircuit(nodep, /*isOr=*/true); }
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void visit(AstLogEq* nodep) override { unsupported_visit(nodep); }
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void visit(AstLogIf* nodep) override { unsupported_visit(nodep); }
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void visit(AstCond* nodep) override { unsupported_visit(nodep); }
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@ -338,11 +394,12 @@ class LinkIncVisitor final : public VNVisitor {
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}
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void prepost_expr_visit(AstNodeUniop* const nodep) {
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iterateChildren(nodep);
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if (m_unsupportedHere) {
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if (m_condEvalContext && !m_incCondp) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: Pre/post increment/decrement operator"
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" within a logical expression (&&, ||, ?:, etc.)");
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return;
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}
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const bool needGating = m_condEvalContext && m_incCondp;
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AstNodeExpr* const readp = nodep->lhsp();
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AstNodeExpr* const writep = nodep->lhsp()->cloneTreePure(true);
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V3LinkLValue::linkLValueSet(readp, false);
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@ -365,7 +422,19 @@ class LinkIncVisitor final : public VNVisitor {
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// Define what operation will we be doing
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AstNodeExpr* const operp = getOperationp(nodep, readp->cloneTreePure(true), newconstp);
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if (VN_IS(nodep, PreInc) || VN_IS(nodep, PreDec)) {
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if (needGating) {
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// Short-circuit context: mutate the variable only when the gate is true.
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// The temp holds the old value, plus the new value for pre-inc/dec.
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AstAssign* const assignp = new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE},
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readp->cloneTreePure(true)};
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AstNode* const incp = new AstAssign{fl, writep, operp};
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if (VN_IS(nodep, PreInc) || VN_IS(nodep, PreDec)) {
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incp->addNext(new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE},
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readp->cloneTreePure(true)});
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}
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assignp->addNextHere(new AstIf{fl, m_incCondp->cloneTreePure(true), incp, nullptr});
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insertBeforeStmt(nodep, assignp);
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} else if (VN_IS(nodep, PreInc) || VN_IS(nodep, PreDec)) {
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// PreInc/PreDec operations
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// Immediately after declaration - increment it by one
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AstAssign* const assignp
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@ -1,23 +1,26 @@
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%Error-UNSUPPORTED: t/t_increment_bad.v:19:29: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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19 | if (0 && test_string[pos++] != "e");
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| ^~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_increment_bad.v:20:17: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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20 | if (1 || pos-- != 1);
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| ^~
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%Error-UNSUPPORTED: t/t_increment_bad.v:22:15: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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22 | if (a <-> --b);
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| ^~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_increment_bad.v:23:14: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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23 | if (0 -> ++b);
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| ^~
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%Error-UNSUPPORTED: t/t_increment_bad.v:25:22: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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25 | pos = (a > 0) ? a++ : --b;
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%Error-UNSUPPORTED: t/t_increment_bad.v:26:24: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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26 | if (1 && (a > 0 ? a++ : --b));
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| ^~
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%Error-UNSUPPORTED: t/t_increment_bad.v:26:29: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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26 | if (1 && (a > 0 ? a++ : --b));
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| ^~
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%Error-UNSUPPORTED: t/t_increment_bad.v:27:24: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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27 | if (0 || (a > 0 -> ++b));
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| ^~
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%Error-UNSUPPORTED: t/t_increment_bad.v:29:22: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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29 | pos = (a > 0) ? a++ : --b;
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| ^~
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%Error-UNSUPPORTED: t/t_increment_bad.v:25:27: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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25 | pos = (a > 0) ? a++ : --b;
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%Error-UNSUPPORTED: t/t_increment_bad.v:29:27: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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29 | pos = (a > 0) ? a++ : --b;
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| ^~
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%Error-UNSUPPORTED: t/t_increment_bad.v:30:36: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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30 | assert property (@(posedge clk) a++ >= 0);
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%Error-UNSUPPORTED: t/t_increment_bad.v:34:36: Unsupported: Pre/post increment/decrement operator within a logical expression (&&, ||, ?:, etc.)
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34 | assert property (@(posedge clk) a++ >= 0);
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| ^~
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%Error: Exiting due to
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@ -22,6 +22,10 @@ module t (
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if (a <-> --b);
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if (0 -> ++b);
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// ++/-- nested in ?:/-> inside a supported &&/|| must still error
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if (1 && (a > 0 ? a++ : --b));
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if (0 || (a > 0 -> ++b));
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pos = (a > 0) ? a++ : --b;
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pos = array[0][0]++;
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,182 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Test inline pre/post increment/decrement operators, including
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// inside logical operators (&&, ||) with short-circuit semantics.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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integer a, b, c;
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reg cond;
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int side;
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// Impure (side-effecting) function for use as a short-circuit LHS
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function automatic int bump();
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side = side + 1;
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return 1;
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endfunction
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// ++/-- in && / || inside a function/task exercises the function-local temp
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function automatic int f_and(int x);
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if (x > 0 && x++ < 100) ;
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return x;
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endfunction
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function automatic int f_or(int x);
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if (x > 0 || x++ < 100) ;
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return x;
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endfunction
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// LHS reads the gated variable; must see the pre-increment value exactly once
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function automatic int f_single(int x);
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int taken = 0;
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if (x == 4 && x++ < 100) taken = 1;
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return taken * 1000 + x;
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endfunction
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initial begin
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// ---- Basic post/pre increment/decrement ----
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a = 5; b = a++; `checkh(b, 5); `checkh(a, 6);
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a = 5; b = ++a; `checkh(a, 6); `checkh(b, 6);
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a = 10; b = 5; b = a++ + b; `checkh(b, 15); `checkh(a, 11);
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a = 10; b = 5; b = ++a + b; `checkh(b, 16); `checkh(a, 11);
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a = 7; b = a++ * 2; `checkh(b, 14); `checkh(a, 8);
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a = 7; b = ++a * 2; `checkh(b, 16); `checkh(a, 8);
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a = 3; b = 4; c = a++ + b++; `checkh(c, 7); `checkh(a, 4); `checkh(b, 5);
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a = 3; b = 4; c = ++a + ++b; `checkh(c, 9); `checkh(a, 4); `checkh(b, 5);
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a = 10; b = 3; c = a++ - b--; `checkh(c, 7); `checkh(a, 11); `checkh(b, 2);
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a = 5; b = 5; b = a--; `checkh(b, 5); `checkh(a, 4);
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a = 5; b = --a; `checkh(b, 4); `checkh(a, 4);
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// ---- Post-inc in shift (5 << 5 = 160) ----
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a = 5; b = 5; b = b << a++; `checkh(b, 160); `checkh(a, 6);
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// ---- Post-inc in paren expr ----
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a = 2; b = (a++ + 1) * 3; `checkh(b, 9); `checkh(a, 3);
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// ---- Post-inc in while with && (constant) ----
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a = 0; while (1 && a++ < 3) begin end `checkh(a, 4);
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// ---- Post-inc in while with && (variable cond, non-short-circuit) ----
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cond = 1; a = 0; while (cond && a++ < 3) begin end `checkh(a, 4);
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// ---- Post-inc in while with && (variable cond, short-circuit) ----
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cond = 0; a = 0; while (cond && a++ < 3) begin end `checkh(a, 0);
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// ---- Post-inc in while with || ----
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a = 0; while (0 || a++ < 3) begin end `checkh(a, 4);
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// ---- && short-circuit ----
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a = 0; if (0 && a++ < 3) begin end `checkh(a, 0);
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// ---- && non-short-circuit ----
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a = 0; if (1 && a++ < 5) begin end `checkh(a, 1);
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// ---- || non-short-circuit ----
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a = 0; if (0 || a++ < 5) begin end `checkh(a, 1);
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// ---- || short-circuit ----
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a = 0; if (1 || a++ < 5) begin end `checkh(a, 0);
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// ---- Pre-inc with && ----
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a = 0; if (1 && ++a < 5) begin end `checkh(a, 1);
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// ---- Pre-inc short-circuit ----
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a = 0; if (0 && ++a < 5) begin end `checkh(a, 0);
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// ---- Pre-inc with || ----
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a = 0; if (0 || ++a < 5) begin end `checkh(a, 1);
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a = 0; if (1 || ++a < 5) begin end `checkh(a, 0);
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// ---- Nested && chain ----
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a = 0; if (1 && 1 && a++ < 5) begin end `checkh(a, 1);
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// ---- Post-dec with && ----
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a = 5; if (1 && a-- > 0) begin end `checkh(a, 4);
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// ---- Pre-dec with && short-circuit ----
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a = 5; if (0 && --a > 0) begin end `checkh(a, 5);
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// ---- Post-dec with || ----
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a = 5; if (0 || a-- > 0) begin end `checkh(a, 4);
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a = 5; if (1 || a-- > 0) begin end `checkh(a, 5);
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// ---- Pre-dec with || ----
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a = 5; if (0 || --a > 0) begin end `checkh(a, 4);
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// ---- Multiple increments in && chain ----
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a = 0; b = 0;
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if (1 && a++ < 5 && b++ < 5) begin end
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`checkh(a, 1); `checkh(b, 1);
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// ---- Post-inc on left side of && ----
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a = 0; if (a++ < 5 && 1) begin end `checkh(a, 1);
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// ---- Post-inc on left side of || ----
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a = 0; if (a++ < 5 || 0) begin end `checkh(a, 1);
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// ---- Pre-inc on left side of || ----
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a = 0; if (++a < 5 || 0) begin end `checkh(a, 1);
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// ---- Mixed && and || with post-inc ----
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a = 0; b = 0;
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if (1 && a++ < 5 || b++ < 5) begin end
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`checkh(a, 1); `checkh(b, 0);
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a = 0; b = 0;
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if (0 && a++ < 5 || b++ < 5) begin end
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`checkh(a, 0); `checkh(b, 1);
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// ---- Deep nesting (3 levels &&) ----
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a = 0; b = 0; c = 0;
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if (1 && 1 && a++ < 5 && b++ < 5 && c++ < 5) begin end
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`checkh(a, 1); `checkh(b, 1); `checkh(c, 1);
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a = 0; b = 0; c = 0;
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if (1 && 0 && a++ < 5 && b++ < 5 && c++ < 5) begin end
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`checkh(a, 0); `checkh(b, 0); `checkh(c, 0);
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// ---- LHS reads variable that gated RHS ++/-- writes (single-eval) ----
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a = 4; if (a == 4 && a++ < 10) begin end `checkh(a, 5);
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a = 6; if (a == 4 && a++ < 10) begin end `checkh(a, 6);
|
||||
a = 0; if (a < 1 && a++ < 5) begin end `checkh(a, 1);
|
||||
a = 5; if (a > 0 && a-- > 0) begin end `checkh(a, 4);
|
||||
a = 4; if (a == 4 && ++a < 10) begin end `checkh(a, 5);
|
||||
|
||||
// ---- || mirror: LHS reads variable that gated RHS modifies ----
|
||||
a = 4; if (a != 4 || a++ < 10) begin end `checkh(a, 5);
|
||||
a = 6; if (a != 4 || a++ < 10) begin end `checkh(a, 6);
|
||||
|
||||
// ---- Nested gate: inner && with non-const LHS inside an outer gate ----
|
||||
a = 4; if (a == 4 && (a < 10 && a++ < 20)) begin end `checkh(a, 5);
|
||||
a = 20; if (a == 20 && (a < 10 && a++ < 30)) begin end `checkh(a, 20);
|
||||
a = 0; if (a == 4 && (a < 10 && a++ < 20)) begin end `checkh(a, 0);
|
||||
|
||||
// ---- ++/-- in && / || inside a function (function-local temp) ----
|
||||
`checkh(f_and(5), 6); // 5>0 true, post-inc runs -> 6
|
||||
`checkh(f_and(0), 0); // 0>0 false, short-circuit -> unchanged
|
||||
`checkh(f_or(5), 5); // 5>0 true, short-circuit -> unchanged
|
||||
`checkh(f_or(0), 1); // 0>0 false, post-inc runs -> 1
|
||||
`checkh(f_single(4), 1005); // 4==4 (once) && 4<100 -> taken=1, x=5
|
||||
`checkh(f_single(6), 6); // 6==4 false, short-circuit -> taken=0, x=6
|
||||
|
||||
// ---- Impure (side-effecting) LHS must be evaluated exactly once ----
|
||||
side = 0; a = 0; if (bump() > 0 && a++ < 5) begin end `checkh(side, 1); `checkh(a, 1);
|
||||
side = 0; a = 0; if (bump() < 0 && a++ < 5) begin end `checkh(side, 1); `checkh(a, 0);
|
||||
|
||||
// ---- ++/-- on LHS, side-effecting function on opposite (RHS) side ----
|
||||
side = 0; a = 0; if (a++ < 5 && bump() > 0) begin end `checkh(a, 1); `checkh(side, 1);
|
||||
side = 0; a = 0; if (a++ > 5 && bump() > 0) begin end `checkh(a, 1); `checkh(side, 0);
|
||||
side = 0; a = 0; if (a++ > 5 || bump() > 0) begin end `checkh(a, 1); `checkh(side, 1);
|
||||
side = 0; a = 0; if (a++ < 5 || bump() > 0) begin end `checkh(a, 1); `checkh(side, 0);
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue