luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix HIERPARAM to be suppressed for interface ports (#6587) (#6609)

Browse Source 
Co-authored-by: Paul Swirhun <[email protected]>
This commit is contained in:
Paul Swirhun
2025-10-31 15:49:30 -04:00
committed by GitHub
co-authored by Paul Swirhun
parent 922223a9c3
commit 10935ee031
10 changed files with 266 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
test_regress/t/t_interface_array_parameter_access.v
+6 -4
View File
@@ -11,13 +11,13 @@ interface intf
modport modp (input clk, rst);
endinterface
module sub (intf.modp the_intf_port [4]);
// verilator lint_off HIERPARAM
module sub (intf.modp the_intf_port [4], intf.modp single_intf_port);
localparam intf_foo = the_intf_port[0].FOO;
// verilator lint_on HIERPARAM
localparam single_foo = single_intf_port.FOO;
initial begin
if (intf_foo != 4) $stop;
if (single_foo != 4) $stop;
end
endmodule
@@ -28,10 +28,12 @@ module t (
input clk;
intf the_intf [4] (.*);
intf single_intf (.*);
sub
the_sub (
.the_intf_port (the_intf)
.the_intf_port (the_intf),
.single_intf_port(single_intf)
);
always @(posedge clk) begin