Fix segfault when modport variable is unresolved (#6386)

src/V3LinkDot.cpp

@@ -3916,6 +3916,15 @@ class LinkDotResolveVisitor final : public VNVisitor {
             }
             dotSymp = m_statep->findDotted(nodep->fileline(), dotSymp, nodep->dotted(), baddot,
                                            okSymp, true);  // Maybe nullptr
+            if (!dotSymp) {
+                nodep->v3error(
+                    "Can't find definition of "
+                    << (!baddot.empty() ? AstNode::prettyNameQ(baddot) : nodep->prettyNameQ())
+                    << '\n'
+                    << nodep->warnContextPrimary());
+                return;
+            }
+
             bool modport = false;
             if (const AstVar* varp = VN_CAST(dotSymp->nodep(), Var)) {
                 if (const AstIfaceRefDType* const ifaceRefp

test_regress/t/t_mod_interface_clocking_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_mod_interface_clocking_bad.v:25:10: Can't find definition of 'cb'
+   25 |     x.cb.reset <= 1;
+      |          ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to

test_regress/t/t_mod_interface_clocking_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_mod_interface_clocking_bad.v

@@ -0,0 +1,35 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+interface mem_if (
+    input wire clk
+);
+  logic reset;
+
+  clocking cb @(posedge clk);
+    output reset;
+  endclocking
+
+  modport mp(input clk);
+
+endinterface
+
+module sub (
+    mem_if.mp x
+);
+
+  initial begin
+    x.cb.reset <= 1;
+  end
+
+endmodule
+
+module t ();
+  logic clk = 0;
+
+  mem_if m_if (clk);
+  sub i_sub (m_if);
+endmodule