mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 01:54:01 +02:00
Internals: Remove extra single-line {}. No functional change.
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+5
-5
@@ -105,7 +105,7 @@ V3Number::V3Number(VerilogStringLiteral, AstNode* nodep, const string& str) {
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const int topos = str.length() - 1 - pos;
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ValueAndX& v = m_data.num()[topos / 4];
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for (int bit = 0; bit < 8; ++bit) {
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if (str[pos] & (1UL << bit)) { v.m_value |= (1UL << (bit + (topos % 4) * 8)); }
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if (str[pos] & (1UL << bit)) v.m_value |= (1UL << (bit + (topos % 4) * 8));
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}
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}
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}
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@@ -991,7 +991,7 @@ V3Hash V3Number::toHash() const {
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if (isString()) {
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hash += V3Hash{m_data.str()};
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} else {
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for (int i = 0; i < words(); ++i) { hash += m_data.num()[i].m_value; }
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for (int i = 0; i < words(); ++i) hash += m_data.num()[i].m_value;
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}
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return hash;
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}
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@@ -2053,7 +2053,7 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool
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uint32_t vn[VL_MULS_MAX_WORDS + 1]; // v normalized
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// Zero for ease of debugging and to save having to zero for shifts
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for (int i = 0; i < words; i++) { m_data.num()[i].m_value = 0; }
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for (int i = 0; i < words; i++) m_data.num()[i].m_value = 0;
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for (int i = 0; i < words + 1; i++) { un[i] = vn[i] = 0; } // +1 as vn may get extra word
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// Algorithm requires divisor MSB to be set
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@@ -2270,7 +2270,7 @@ V3Number& V3Number::opExtendXZ(const V3Number& lhs, uint32_t lbits) {
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NUM_ASSERT_OP_ARGS1(lhs);
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NUM_ASSERT_LOGIC_ARGS1(lhs);
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setZero();
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for (int bit = 0; bit < width(); bit++) { setBit(bit, lhs.bitIsExtend(bit, lbits)); }
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for (int bit = 0; bit < width(); bit++) setBit(bit, lhs.bitIsExtend(bit, lbits));
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return *this;
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}
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@@ -2499,7 +2499,7 @@ V3Number& V3Number::opReplN(const V3Number& lhs, uint32_t rhsval) {
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NUM_ASSERT_STRING_ARGS1(lhs);
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string out;
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out.reserve(lhs.toString().length() * rhsval);
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for (unsigned times = 0; times < rhsval; times++) { out += lhs.toString(); }
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for (unsigned times = 0; times < rhsval; times++) out += lhs.toString();
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return setString(out);
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}
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V3Number& V3Number::opToLowerN(const V3Number& lhs) {
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