Fix enums in port crossings and function arguments

src/V3AstNodes.h

@@ -265,7 +265,7 @@ public:
     virtual AstBasicDType* basicp() const { return defp() ? dtypep()->basicp() : NULL; }
     virtual AstNodeDType* skipRefp() const {
 	// Skip past both the Ref and the Typedef
-	if (defp()) return defp()->dtypep();
+	if (defp()) return defp()->dtypep()->skipRefp();
 	else { v3fatalSrc("Typedef not linked"); return NULL; }
     }
     virtual int widthAlignBytes() const { return dtypep()->widthAlignBytes(); }
@@ -335,7 +335,7 @@ struct AstEnumDType : public AstNodeDType {
     void addValuesp(AstNode* nodep) { addOp2p(nodep); }
     // METHODS
     virtual AstBasicDType* basicp() const { return dtypep()->basicp(); }  // (Slow) recurse down to find basic data type
-    virtual AstNodeDType* skipRefp() const { return (AstNodeDType*)this; }
+    virtual AstNodeDType* skipRefp() const { return dtypep()->skipRefp(); }
     virtual int widthAlignBytes() const { return dtypep()->widthAlignBytes(); }
     virtual int widthTotalBytes() const { return dtypep()->widthAlignBytes(); }
 };

test_regress/t/t_enum_func.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_enum_func.v

@@ -0,0 +1,65 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+typedef enum { EN_ZERO,
+	       EN_ONE
+	       } En_t;
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   // Insure that we can declare a type with a function declaration
+   function enum integer {
+			  EF_TRUE = 1,
+			  EF_FALSE = 0 }
+				    f_enum_inv ( input a);
+      f_enum_inv = a ? EF_FALSE : EF_TRUE;
+   endfunction
+   initial begin
+      if (f_enum_inv(1) != 0) $stop;
+      if (f_enum_inv(0) != 1) $stop;
+   end
+
+   En_t a, z;
+
+   sub sub (/*AUTOINST*/
+	    // Outputs
+	    .z				(z),
+	    // Inputs
+	    .a				(a));
+
+   integer    cyc; initial cyc=1;
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+	 cyc <= cyc + 1;
+	 if (cyc==1) begin
+	    a <= EN_ZERO;
+	 end
+	 if (cyc==2) begin
+	    a <= EN_ONE;
+	    if (z != EN_ONE) $stop;
+	 end
+	 if (cyc==3) begin
+	    if (z != EN_ZERO) $stop;
+	 end
+	 if (cyc==9) begin
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   end
+
+endmodule
+
+module sub (input En_t a, output En_t z);
+   always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:

test_regress/t/t_sys_sformat.v

@@ -31,7 +31,11 @@ module t;
 
       $swrite(str2, "mod=%m");
 `ifdef TEST_VERBOSE  $display("str2=%0s",str2);  `endif
+`ifdef verilator
       if (str2 !== "mod=top.v") $stop;
+`else
+      if (str2 !== "mod=top.t") $stop;
+`endif
 
       $write("*-* All Finished *-*\n");
       $finish;