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Optimize V3Gate inlining heuristic (#7716)
V3Gate used to inline too many expensive operations. One particularly
bad example is inlining `{<<{wide}}` (bit-reverse of a wide signal),
which is a single input node, but is quite expensive to compute, which
we always used to inline.
Change the heuristic to only inline single input nodes if they are not
wide, or a cheap wide operation, otherwise treat them the same as
multi-input ops and inline them only if they are used no more than once.
This commit is contained in:
Geza Lore
+41
-68
@@ -543,89 +543,62 @@ class GateInline final {
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// Logic block with pending substitutions are stored in this map, together with their ordinal
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std::unordered_map<AstNode*, size_t> m_hasPending;
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size_t m_statInlined = 0; // Statistic tracking - signals inlined
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size_t m_statRefs = 0; // Statistic tracking
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size_t m_statExcluded = 0; // Statistic tracking
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size_t m_statNotInlined = 0; // Statistic tracking - signals not inlined due to cost
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size_t m_statRefs = 0; // Statistic tracking - number of input variable references replaced
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// METHODS
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static bool isCheapWide(const AstNodeExpr* exprp) {
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static bool isCheap(const AstNodeExpr* exprp) {
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// Constant is cheap
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if (VN_IS(exprp, Const)) return true;
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// Variable reference is cheap
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if (VN_IS(exprp, NodeVarRef)) return true;
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// AstSel is cheap if the fromp is cheap, and not a wide needing bit swizzling
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if (const AstSel* const selp = VN_CAST(exprp, Sel)) {
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if (!isCheap(selp->fromp())) return false;
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if (!selp->isWide()) return true;
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if (!VN_IS(selp->lsbp(), Const)) return false;
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if (selp->lsbConst() % VL_EDATASIZE != 0) return false;
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exprp = selp->fromp();
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return true;
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}
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if (const AstArraySel* const aselp = VN_CAST(exprp, ArraySel)) exprp = aselp->fromp();
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return VN_IS(exprp, Const) || VN_IS(exprp, NodeVarRef);
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}
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static bool excludedWide(GateVarVertex* const vVtxp, const AstNodeExpr* const rhsp) {
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// Handle wides with logic drivers that are too wide for V3Expand.
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if (!vVtxp->varScp()->isWide() //
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|| vVtxp->varScp()->widthWords() <= v3Global.opt.expandLimit() //
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|| vVtxp->inEmpty() //
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|| isCheapWide(rhsp))
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return false;
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const GateLogicVertex* const lVtxp
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= vVtxp->inEdges().frontp()->fromp()->as<GateLogicVertex>();
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// Exclude from inlining variables READ multiple times.
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// To decouple actives thus simplifying scheduling, exclude only those
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// VarRefs that are referenced under the same active as they were assigned.
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if (const AstActive* const primaryActivep = lVtxp->activep()) {
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size_t reads = 0;
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for (const V3GraphEdge& edge : vVtxp->outEdges()) {
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const GateLogicVertex* const lvp = edge.top()->as<GateLogicVertex>();
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if (lvp->activep() != primaryActivep) continue;
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reads += edge.weight();
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if (reads > 1) return true;
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}
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// AstArraySel is cheap if the fromp is cheap
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if (const AstArraySel* const aselp = VN_CAST(exprp, ArraySel)) {
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return isCheap(aselp->fromp());
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}
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// Otherwise it is not cheap
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return false;
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}
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bool shouldInline(GateVarVertex* vVtxp, GateLogicVertex* lVtxp, size_t nReads,
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AstNodeExpr* substp, bool allowMultiIn) {
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AstVarScope* const vscp = vVtxp->varScp();
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// Always inline constants
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if (VN_IS(substp, Const)) return true;
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// Don't inline non-constant static initializers
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// Don't inline non-constant static initializers - these are scheduled differently
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if (lVtxp->staticInit()) return false;
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// Inline simple variable references
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if (VN_IS(substp, VarRef)) return true;
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// Only inline arrays if a simple variable or constant
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if (VN_IS(vscp->dtypep()->skipRefp(), UnpackArrayDType)) return false;
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// Inline constant array selects
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if (VN_IS(substp, ArraySel) && nReads <= 1) return true;
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// Don't inline expensive wide operations
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if (excludedWide(vVtxp, substp)) {
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++m_statExcluded;
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UINFO(9, "Gate inline exclude '" << vVtxp->name() << "'");
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vVtxp->clearReducible("Excluded wide"); // Check once.
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return false;
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}
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if (nReads == 0) {
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// Reads no variables, likely unfolded constant expression
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return true;
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} else if (nReads == 1) {
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// Reads one variable
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return true;
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} else {
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// Reads more two or more variables
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if (!allowMultiIn) return false;
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// Do it if not used, or used only once, ignoring slow code
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int n = 0;
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for (V3GraphEdge& edge : vVtxp->outEdges()) {
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const GateLogicVertex* const dstVtxp = edge.top()->as<GateLogicVertex>();
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// Ignore slow code, or if the destination is not used
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if (dstVtxp->slow()) continue;
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if (dstVtxp->outEmpty() && !dstVtxp->consumed()) continue;
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n += edge.weight();
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if (n > 1) return false;
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if (VN_IS(vVtxp->varScp()->dtypep()->skipRefp(), UnpackArrayDType)) return false;
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// Inline if reads no variables - unfolded constant expression, nullary builtin e.g.: $time
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if (nReads == 0) return true;
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// If it reads one variable, inline if not wide, or if cheap
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if (nReads == 1 && (!substp->isWide() || isCheap(substp))) return true;
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// Don't inline on first round if reads more than one variable
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if (nReads > 1 && !allowMultiIn) return false;
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// Reads multiple variables, or is expensive to compute.
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// Inline if used only once, ignoring slow code, or dead code that can be deleted.
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int n = 0;
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for (V3GraphEdge& edge : vVtxp->outEdges()) {
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const GateLogicVertex* const dstVtxp = edge.top()->as<GateLogicVertex>();
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// Ignore slow code, or if the destination is not used
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if (dstVtxp->slow()) continue;
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if (dstVtxp->outEmpty() && !dstVtxp->consumed()) continue;
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n += edge.weight();
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if (n > 1) {
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++m_statNotInlined;
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return false;
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}
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return true;
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}
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return true;
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}
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void recordSubstitution(AstVarScope* vscp, AstNodeExpr* substp, AstNode* logicp) {
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@@ -724,7 +697,7 @@ class GateInline final {
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if (!okVisitor.varAssigned(vVtxp->varScp())) continue;
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// Expression we are considering to substitute with
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AstNodeExpr* const substp = okVisitor.substitutionp();
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AstNodeExpr* const substp = V3Const::constifyEdit(okVisitor.substitutionp());
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// Number of variables read by the substitution
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const size_t nReads = okVisitor.readVscps().size();
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@@ -832,9 +805,9 @@ class GateInline final {
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}
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~GateInline() {
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V3Stats::addStat("Optimizations, Gate sigs deleted", m_statInlined);
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V3Stats::addStat("Optimizations, Gate inputs replaced", m_statRefs);
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V3Stats::addStat("Optimizations, Gate excluded wide expressions", m_statExcluded);
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V3Stats::addStat("Optimizations, Gate signals inlined", m_statInlined);
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V3Stats::addStat("Optimizations, Gate signals not inlined due to cost", m_statNotInlined);
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V3Stats::addStat("Optimizations, Gate reads replaced", m_statRefs);
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}
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public:
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