Update test

Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>

test_regress/t/t_fork_write_after_timing.py

@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--Wno-initialdly", "--binary"])
+test.compile(verilator_flags2=["--binary"])
 
 test.execute(expect_filename=test.golden_filename)
 

test_regress/t/t_fork_write_after_timing.v

@@ -21,8 +21,6 @@ module t;
     t2(x1);
     t3(x1);
     t4(x1);
-    t5(x2);
-    t6(x2);
 
     #5 $write("*-* All Finished *-*\n");
     $finish;
@@ -59,13 +57,4 @@ module t;
     join_none
     #2 $display("t4 end %d", x);
   endtask
-
-  task t5(output int x);
-    if (x != 0) $stop;
-    x <= #1 3;
-  endtask
-
-  task t6(inout int x);
-    x <= #1 4;
-  endtask
 endmodule