Add error on non-packed struct randc (#5999).
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@ -13,6 +13,7 @@ Verilator 5.041 devel
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**Other:**
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**Other:**
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* Add error on non-packed struct randc (#5999). [Seth Pellegrino]
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* Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore]
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* Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore]
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* Improve `covergroup with function sample` handling (#6387). [Jakub Wasilewski]
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* Improve `covergroup with function sample` handling (#6387). [Jakub Wasilewski]
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* Optimize dead functions without references (#6380). [Artur Bieniek, Antmicro Ltd.]
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* Optimize dead functions without references (#6380). [Artur Bieniek, Antmicro Ltd.]
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@ -1602,9 +1602,7 @@ class RandomizeVisitor final : public VNVisitor {
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if (AstEnumDType* const enumDtp = VN_CAST(varp->dtypep()->skipRefToEnump(), EnumDType)) {
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if (AstEnumDType* const enumDtp = VN_CAST(varp->dtypep()->skipRefToEnump(), EnumDType)) {
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items = static_cast<uint64_t>(enumDtp->itemCount());
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items = static_cast<uint64_t>(enumDtp->itemCount());
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} else {
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} else if (AstBasicDType* const basicp = varp->dtypep()->skipRefp()->basicp()) {
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AstBasicDType* const basicp = varp->dtypep()->skipRefp()->basicp();
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UASSERT_OBJ(basicp, varp, "Unexpected randc variable dtype");
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if (basicp->width() > 32) {
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if (basicp->width() > 32) {
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varp->v3error("Maximum implemented width for randc is 32 bits, "
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varp->v3error("Maximum implemented width for randc is 32 bits, "
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<< varp->prettyNameQ() << " is " << basicp->width() << " bits");
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<< varp->prettyNameQ() << " is " << basicp->width() << " bits");
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@ -1612,6 +1610,13 @@ class RandomizeVisitor final : public VNVisitor {
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return nullptr;
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return nullptr;
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}
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}
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items = 1ULL << basicp->width();
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items = 1ULL << basicp->width();
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} else if (AstStructDType* const dtp = VN_CAST(varp->dtypep()->skipRefp(), StructDType)) {
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UASSERT_OBJ(!dtp->packed(), dtp, "skipRef should have hidden packed before got here");
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dtp->v3error("Unpacked structs shall not be declared as randc"
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" (IEEE 1800-2023 18.4)");
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return nullptr;
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} else {
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varp->v3fatalSrc("Unexpected randc variable dtype");
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}
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}
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AstCDType* newdtp = findVlRandCDType(varp->fileline(), items);
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AstCDType* newdtp = findVlRandCDType(varp->fileline(), items);
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AstVar* newp
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AstVar* newp
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@ -0,0 +1,5 @@
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%Error: t/t_randomize_unpacked_bad.v:8:9: Unpacked structs shall not be declared as randc (IEEE 1800-2023 18.4)
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8 | randc struct {logic m_x;} s;
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| ^~~~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,18 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class ex;
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randc struct {logic m_x;} s; // <--- Bad: randc illegal on unpacked struct
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randc struct packed {logic m_x;} p_s; // Ok
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endclass : ex
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module foo;
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initial begin
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ex e;
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void'(e.randomize());
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end
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endmodule
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