Add -Wall reporting ASSIGNDLY on assignment delays.

Changes

@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Add configure options for cc warnings and extended tests.  [Ruben Diez]
 
+***  Add -Wall reporting ASSIGNDLY on assignment delays.  [Ruben Diez]
+
 ***  Fix UNDRIVEN warnings inside DPI import functions.  [Ruben Diez]
 
 ***  Fix --help output to go to stderr, not stdout, bug397.  [Ruben Diez]

bin/verilator

@@ -943,8 +943,8 @@ enabled), but do not affect style messages.  This is equivalent to
 =item -Wwarn-style
 
 Enable all code style related warning messages.  This is equivalent to
-"-Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-INCABSPATH -Wwarn-SYNCASYNCNET
+"-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-INCABSPATH
--Wwarn-UNDRIVEN -Wwarn-UNUSED -Wwarn-VARHIDDEN".
+-Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN -Wwarn-UNUSED -Wwarn-VARHIDDEN".
 
 =item -x-assign 0
 
@@ -2377,6 +2377,18 @@ List of all warnings:
 
 =over 4
 
+=item ASSIGNDLY
+
+Warns that you have an assignment statement with a delayed time in front of
+it, for example:
+
+    a <= #100 b;
+    assign #100 a = b;
+
+Ignoring this warning may make Verilator simulations differ from other
+simulators, however at one point this was a common style so disabled by
+default as a code style warning.
+
 =item BLKANDNBLK
 
 BLKANDNBLK is an error that a variable comes from a mix of blocked and

src/V3Error.h

@@ -55,6 +55,7 @@ public:
 	// Warning codes:
 	EC_FIRST_WARN,	// Just a code so the program knows where to start warnings
 	//
+	ASSIGNDLY,	// Assignment delays
 	BLKANDNBLK,	// Blocked and non-blocking assignments to same variable
 	BLKSEQ,		// Blocking assignments in sequential block
 	CASEINCOMPLETE,	// Case statement has missing values
@@ -107,6 +108,7 @@ public:
 	    "MULTITOP", "TASKNSVAR", "BLKLOOPINIT",
 	    // Warnings
 	    " EC_FIRST_WARN",
+	    "ASSIGNDLY",
 	    "BLKANDNBLK", "BLKSEQ",
 	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CDCRSTLOGIC", "CMPCONST",
 	    "COMBDLY", "DEFPARAM", "DECLFILENAME",
@@ -142,7 +144,8 @@ public:
 				      || m_e==UNSIGNED
 				      || m_e==WIDTH); }
     // Warnings that are style only
-    bool styleError() const { return ( m_e==BLKSEQ
+    bool styleError() const { return ( m_e==ASSIGNDLY  // More than style, but for backward compatibility
+				       || m_e==BLKSEQ
 				       || m_e==DEFPARAM
 				       || m_e==DECLFILENAME
 				       || m_e==INCABSPATH

src/verilog.y

@@ -1527,7 +1527,7 @@ assignOne<nodep>:
 
 delayE:
 		/* empty */				{ }
-	|	delay_control				{ } /* ignored */
+	|	delay_control				{ $1->v3warn(ASSIGNDLY,"Ignoring delay on this assignment/primitive."); } /* ignored */
 	;
 
 delay_control<fl>:	//== IEEE: delay_control

test_regress/t/t_delay.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 compile (
-	 verilator_flags2 => ['-Wno-STMTDLY'],
+	 verilator_flags2 => ['-Wno-STMTDLY -Wno-ASSIGNDLY'],
 	 );
 
 execute (

test_regress/t/t_delay.v

@@ -28,6 +28,7 @@ module t (/*AUTOARG*/
       end
       else if (cyc==3) begin
 	 if (dly0 !== 32'h23) $stop;
+	 if (dly2 !== 32'h25) $stop;
 	 $write("*-* All Finished *-*\n");
 	 #100 $finish;
       end

test_regress/t/t_delay_stmtdly_bad.pl

@@ -12,9 +12,14 @@ top_filename("t/t_delay.v");
 $Self->{vlt} or $Self->skip("Verilator only test");
 
 compile (
+	 verilator_flags2 => ['-Wall -Wno-DECLFILENAME'],
 	 fails=>1,
 	 expect=>
-'%Warning-STMTDLY: t/t_delay.v:\d+: Ignoring delay on this delayed statement.
+'%Warning-ASSIGNDLY: t/t_delay.v:\d+: Ignoring delay on this assignment/primitive.
+%Warning-ASSIGNDLY: Use .*
+%Warning-ASSIGNDLY: t/t_delay.v:\d+: Ignoring delay on this assignment/primitive.
+%Warning-ASSIGNDLY: t/t_delay.v:\d+: Ignoring delay on this assignment/primitive.
+%Warning-STMTDLY: t/t_delay.v:\d+: Ignoring delay on this delayed statement.
 .*%Error: Exiting due to.*',
 	 );