Fix the SC_MODULE name() to not include __PVT__, for nicer coverage.

Changes

@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.70****
+
+**** Fix the SC_MODULE name() to not include __PVT__.  [Bob Fredieu]
+
 * Verilator 3.701 2009/02/26
 
 **   Support repeat and forever statements.  [Jeremy Bennett]

src/V3EmitCSyms.cpp

@@ -207,11 +207,9 @@ void EmitCSyms::emitImp() {
 	AstScope* scopep = it->first;  AstModule* modp = it->second;
 	if (modp->isTop()) {
 	} else {
-	    string arrow = scopep->name();
-	    if (arrow.substr(0,4) == "TOP.") arrow.replace(0,4,".");
 	    ofp()->printf("\t%c %-30s ", comma, scopep->nameDotless().c_str());
 	    puts("(Verilated::catName(topp->name(),\"");
-	    puts(arrow);
+	    puts("."+scopep->prettyName());
 	    puts("\"))\n");
 	    comma=',';
 	}

test_regress/t/t_cover_sva_notflat.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => [$Self->{v3}?'--assert --sp --coverage-user':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+#if ($Self->{nc}) ... # See t_assert_cover.pl for NC version
+
+# Allow old Perl format dump, or new binary dump
+# Check that the hierarchy doesn't include __PVT__
+# Otherwise our coverage reports would look really ugly
+file_grep ($Self->{coverage_filename}, qr/(TOP\.v\.sub.*.cyc_eq_5)/);
+
+ok(1);
+1;

test_regress/t/t_cover_sva_notflat.v

@@ -0,0 +1,59 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   reg 	 toggle;
+   integer cyc; initial cyc=1;
+
+   Test suba (/*AUTOINST*/
+	      // Inputs
+	      .clk			(clk),
+	      .toggle			(toggle),
+	      .cyc			(cyc[31:0]));
+   Test subb (/*AUTOINST*/
+	      // Inputs
+	      .clk			(clk),
+	      .toggle			(toggle),
+	      .cyc			(cyc[31:0]));
+   Test subc (/*AUTOINST*/
+	      // Inputs
+	      .clk			(clk),
+	      .toggle			(toggle),
+	      .cyc			(cyc[31:0]));
+
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+	 cyc <= cyc + 1;
+	 toggle <= !cyc[0];
+	 if (cyc==9) begin
+	 end
+	 if (cyc==10) begin
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   end
+
+endmodule
+
+module Test
+  (
+   input clk,
+   input toggle,
+   input [31:0] cyc
+   );
+
+   // Don't flatten out these modules please:
+   // verilator no_inline_module
+
+   // Labeled cover
+   cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); 
+
+endmodule