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Fix incorrect code generation for change expression on typedefed unpacked array (#4915)

This commit is contained in:
Geza Lore 2024-02-23 08:53:42 +00:00 committed by GitHub
parent 5964d5cf63
commit 0892b39ad2
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GPG Key ID: B5690EEEBB952194
3 changed files with 36 additions and 6 deletions
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5
src/V3SenExprBuilder.h
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@ -139,7 +139,8 @@ class SenExprBuilder final {
return prevp; return prevp;
} }
if (AstUnpackArrayDType* const dtypep = VN_CAST(exprp->dtypep(), UnpackArrayDType)) { if (AstUnpackArrayDType* const dtypep
= VN_CAST(exprp->dtypep()->skipRefp(), UnpackArrayDType)) {
AstCMethodHard* const cmhp = new AstCMethodHard{flp, wrPrev(), "assign", rdCurr()}; AstCMethodHard* const cmhp = new AstCMethodHard{flp, wrPrev(), "assign", rdCurr()};
cmhp->dtypeSetVoid(); cmhp->dtypeSetVoid();
m_postUpdates.push_back(cmhp->makeStmt()); m_postUpdates.push_back(cmhp->makeStmt());
@ -167,7 +168,7 @@ class SenExprBuilder final {
return {nullptr, false}; // We already warn for this in V3LinkResolve return {nullptr, false}; // We already warn for this in V3LinkResolve
case VEdgeType::ET_CHANGED: case VEdgeType::ET_CHANGED:
case VEdgeType::ET_HYBRID: // case VEdgeType::ET_HYBRID: //
if (VN_IS(senp->dtypep(), UnpackArrayDType)) { if (VN_IS(senp->dtypep()->skipRefp(), UnpackArrayDType)) {
AstCMethodHard* const resultp = new AstCMethodHard{flp, currp(), "neq", prevp()}; AstCMethodHard* const resultp = new AstCMethodHard{flp, currp(), "neq", prevp()};
resultp->dtypeSetBit(); resultp->dtypeSetBit();
return {resultp, true}; return {resultp, true};

13
test_regress/t/t_unopt_array.v
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@ -74,18 +74,23 @@ module Test (/*AUTOARG*/
input [31:0] in; input [31:0] in;
output wire [31:0] out; output wire [31:0] out;
reg [31:0] stage [3:0]; `ifdef USE_TYPEDEF
typedef reg [3:0][31:0] stage_t [3:0];
stage_t stage;
`else
reg [3:0][31:0] stage [3:0];
`endif
genvar g; genvar g;
generate generate
for (g=0; g<4; g++) begin for (g=0; g<4; g++) begin
always_comb begin always_comb begin
if (g==0) stage[g] = in; if (g==0) stage[g] = {4{in}};
else stage[g] = {stage[g-1][30:0],1'b1}; else stage[g] = {4{stage[g-1][0][30:0],1'b1}};
end end
end end
endgenerate endgenerate
assign out = stage[3]; assign out = stage[3][0];
endmodule endmodule

24
test_regress/t/t_unopt_array_typedef.pl Executable file
View File

@ -0,0 +1,24 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
top_filename("t/t_unopt_array.v");
compile(
verilator_flags2 => ["-Wno-UNOPTFLAT +define+USE_TYPEDEF"],
);
execute(
check_finished => 1,
);
ok(1);
1;