Use vlt as abbreviation to avoid confusion with other simulator
This commit is contained in:
Wilson Snyder
parent
0f8a1e3901
commit
06fba42858
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@ -31,7 +31,7 @@ int main(int argc, char **argv, char **env) {
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cout << "Enabling waves...\n";
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SpTraceVcdCFile* tfp = new SpTraceVcdCFile;
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top->trace (tfp, 99); // Trace 99 levels of hierarchy
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tfp->open ("vl_dump.vcd"); // Open the dump file
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tfp->open ("vlt_dump.vcd"); // Open the dump file
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#endif
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top->reset_l = 1; // Set some inputs
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@ -33,7 +33,7 @@ ifneq ($(NC_ROOT),)
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#PRODUCTS += --nc
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endif
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PRODUCTS += --vl
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PRODUCTS += --vlt
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ifeq ($(VERILATOR_AUTHOR_SITE),1)
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DRIVER_FLAGS += -j 0
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@ -57,8 +57,8 @@ nc:
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######################################################################
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vl:
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$(PERL) driver.pl $(DRIVER_FLAGS) --vl --stop
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vlt:
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$(PERL) driver.pl $(DRIVER_FLAGS) --vlt --stop
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######################################################################
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@ -50,7 +50,7 @@ my $opt_nc;
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my $opt_optimize;
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my $opt_stop;
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my $opt_trace;
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my $opt_vl;
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my $opt_vlt;
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my $opt_vcs;
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my $opt_verbose;
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my $Opt_Verilated_Debug;
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@ -69,8 +69,9 @@ if (! GetOptions (
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"optimize:s" => \$opt_optimize,
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"stop!" => \$opt_stop,
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"trace!" => \$opt_trace,
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"v3!" => \$opt_vl, # Old
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"vl!" => \$opt_vl,
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"v3!" => \$opt_vlt, # Old
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"vl!" => \$opt_vlt, # Old
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"vlt!" => \$opt_vlt,
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"vcs!" => \$opt_vcs,
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"verbose!" => \$opt_verbose,
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"verilated_debug!" => \$Opt_Verilated_Debug,
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@ -83,8 +84,8 @@ $opt_jobs = calc_jobs() if defined $opt_jobs && $opt_jobs==0;
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$Fork->max_proc($opt_jobs);
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if (!$opt_iv && !$opt_vcs && !$opt_nc && !$opt_vl) {
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$opt_vl = 1;
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if (!$opt_iv && !$opt_vcs && !$opt_nc && !$opt_vlt) {
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$opt_vlt = 1;
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}
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if ($#opt_tests<0) {
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@ -101,7 +102,7 @@ foreach my $testpl (@opt_tests) {
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one_test(pl_filename => $testpl, iv=>1) if $opt_iv;
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one_test(pl_filename => $testpl, nc=>1) if $opt_nc;
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one_test(pl_filename => $testpl, vcs=>1) if $opt_vcs;
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one_test(pl_filename => $testpl, vl=>1, 'v3'=>1) if $opt_vl;
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one_test(pl_filename => $testpl, vlt=>1, 'v3'=>1) if $opt_vlt;
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}
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$Fork->wait_all(); # Wait for all children to finish
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@ -268,7 +269,7 @@ sub new {
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nc_flags2 => [], # Overridden in some sim files
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ncrun_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")],
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# Verilator
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vl => 0,
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vlt => 0,
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'v3' => 0,
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verilator_flags => ["-cc",
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"-Mdir $self->{obj_dir}",
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@ -281,14 +282,14 @@ sub new {
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bless $self, $class;
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$self->{mode} ||= "vcs" if $self->{vcs};
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$self->{mode} ||= "vl" if $self->{vl};
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$self->{mode} ||= "vlt" if $self->{vlt};
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$self->{mode} ||= "nc" if $self->{nc};
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$self->{mode} ||= "iv" if $self->{iv};
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$self->{VM_PREFIX} ||= "V".$self->{name};
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$self->{stats} ||= "$self->{obj_dir}/V".$self->{name}."__stats.txt";
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$self->{status_filename} ||= "$self->{obj_dir}/V".$self->{name}.".status";
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$self->{run_log_filename} ||= "$self->{obj_dir}/vl_sim.log";
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$self->{coverage_filename} ||= "$self->{obj_dir}/vl_coverage.pl";
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$self->{run_log_filename} ||= "$self->{obj_dir}/vlt_sim.log";
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$self->{coverage_filename} ||= "$self->{obj_dir}/vlt_coverage.pl";
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$self->{vcd_filename} ||= "$self->{obj_dir}/sim.vcd";
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($self->{top_filename} = $self->{pl_filename}) =~ s/\.pl$/\.v/;
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if (!$self->{make_top_shell}) {
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@ -423,7 +424,7 @@ sub compile {
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fails=>$param{fails},
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cmd=>\@cmd);
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}
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if ($param{vl}) {
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if ($param{vlt}) {
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$opt_gdb="gdbrun" if defined $opt_gdb;
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my @verilator_flags = @{$param{verilator_flags}};
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unshift @verilator_flags, "--gdb $opt_gdb" if $opt_gdb;
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@ -464,7 +465,7 @@ sub compile {
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return 1;
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}
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$self->_run(logfile=>"$self->{obj_dir}/vl_compile.log",
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$self->_run(logfile=>"$self->{obj_dir}/vlt_compile.log",
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fails=>$param{fails},
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expect=>$param{expect},
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cmd=>\@vlargs);
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@ -478,7 +479,7 @@ sub compile {
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$self->_sp_preproc(%param);
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}
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$self->oprint("GCC\n");
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$self->_run(logfile=>"$self->{obj_dir}/vl_gcc.log",
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$self->_run(logfile=>"$self->{obj_dir}/vlt_gcc.log",
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cmd=>["cd $self->{obj_dir} && ",
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"make", "-f".getcwd()."/Makefile_obj",
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"VM_PREFIX=$self->{VM_PREFIX}",
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@ -526,10 +527,10 @@ sub execute {
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expect=>undef, # vcs expect isn't the same
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);
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}
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if ($param{vl}
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if ($param{vlt}
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#&& (!$param{needs_v4} || -r "$ENV{VERILATOR_ROOT}/src/V3Gate.cpp")
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) {
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$self->_run(logfile=>"$self->{obj_dir}/vl_sim.log",
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$self->_run(logfile=>"$self->{obj_dir}/vlt_sim.log",
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cmd=>["$self->{obj_dir}/$param{VM_PREFIX}",
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@{$param{all_run_flags}},
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],
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@ -541,7 +542,7 @@ sub execute {
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sub inline_checks {
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my $self = (ref $_[0]? shift : $Self);
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return 1 if $self->errors;
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return 1 if !$self->{vl};
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return 1 if !$self->{vlt};
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my %param = (%{$self}, @_); # Default arguments are from $self
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@ -1179,7 +1180,7 @@ Run using VCS.
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Enable test verbose messages.
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=item --vl
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=item --vlt
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Run using Verilator.
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@ -120,7 +120,7 @@ int sc_main(int argc, char* argv[]) {
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cout << "Enabling waves...\n";
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SpTraceFile* tfp = new SpTraceFile;
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top->trace (tfp, 99);
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tfp->open ("vl_dump.vcd");
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tfp->open ("vlt_dump.vcd");
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#endif
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//==========
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@ -50,7 +50,7 @@ test:: nc
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test:: nonc
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endif
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test:: vl
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test:: vlt
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endif
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vgen.v: ./vgen.pl
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@ -103,7 +103,7 @@ nc_passed.log: vgen.v sim_main.v
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######################################################################
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vl: prep compile vl_passed.log
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vlt: prep compile vlt_passed.log
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prep: vgen.v $(VERILATOR_ROOT)/bin/verilator
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_SW) --cc vgen.v
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@ -111,10 +111,10 @@ prep: vgen.v $(VERILATOR_ROOT)/bin/verilator
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compile:
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cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj
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vl_passed.log vl_run: prep compile
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-rm -f vl_passed.log sim.log
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vlt_passed.log vlt_run: prep compile
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-rm -f vlt_passed.log sim.log
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obj_dir/simx | tee sim.log
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grep -q Finished sim.log && grep Finished sim.log > vl_passed.log
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grep -q Finished sim.log && grep Finished sim.log > vlt_passed.log
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######################################################################
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maintainer-copy::
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