Fix some constant parameter functions causing crash, bug253.

Changes

@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.8****
+
+**** Fix some constant parameter functions causing crash, bug253. [Nick Bowler]
+
 * Verilator 3.802 2010/05/01
 
 ***  Support runtime access to public signal names.

src/V3Param.cpp

@@ -52,10 +52,11 @@
 class ParamVisitor : public AstNVisitor {
 private:
     // NODE STATE
-    //	 AstNodeModule::user4()	// bool	  True if parameters numbered
+    //	 AstNodeModule::user5()	// bool	  True if parameters numbered
     //   AstVar::user4()	// int    Global parameter number (for naming new module)
     //				//        (0=not processed, 1=iterated, but no number, 65+ parameter numbered)
     AstUser4InUse	m_inuser4;
+    AstUser5InUse	m_inuser5;
     // User1/2/3 used by constant function simulations
 
     // STATE
@@ -130,8 +131,8 @@ private:
 
     // Make sure all parameters are constantified
     virtual void visit(AstVar* nodep, AstNUser*) {
-	if (!nodep->user4()) {
-	    nodep->user4(1);  // Mark done - Note values >1 used for letter numbering
+	if (!nodep->user5()) {
+	    nodep->user5(1);  // Mark done
 	    nodep->iterateChildren(*this);
 	    if (nodep->isParam()) {
 		if (!nodep->hasSimpleInit()) { nodep->v3fatalSrc("Parameter without initial value"); }

src/V3Task.cpp

@@ -1034,6 +1034,7 @@ private:
 	AstNodeFTask* funcp = nodep->taskp();
 	if (!funcp) nodep->v3fatalSrc("unlinked");
 	if (!funcp->isFunction()) nodep->v3fatalSrc("func reference to non-function");
+	if (!m_scopep) nodep->v3fatalSrc("func ref not under scope");
 	// Inline func refs in the function
 	iterateIntoFTask(funcp);
 	// Create output variable

test_regress/t/t_param_ceil.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_param_ceil.v

@@ -0,0 +1,55 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		O_out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .O_out			(O_out[31:0]));
+
+   initial begin
+      if (O_out != 32'h4) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module Test
+  (
+   output [31:0] O_out
+   );
+
+   test
+     #(
+       .pFOO(5),
+       .pBAR(2)
+       ) U_test
+       (
+	.O_out(O_out)
+	);
+endmodule
+
+module test
+  #(parameter pFOO = 7,
+    parameter pBAR = 3,
+    parameter pBAZ = ceiling(pFOO, pBAR)
+    )
+   (
+    output [31:0] O_out
+    );
+
+   assign O_out = pBAZ;
+
+   function integer ceiling;
+      input [31:0] x, y;
+      ceiling = ((x%y == 0) ? x/y : (x/y)+1) + 1;
+   endfunction
+endmodule