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https://github.com/verilator/verilator.git
synced 2026-10-06 01:54:01 +02:00
Fix huge shifts to zero with -Wno-WIDTH, bug768.
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+5
-5
@@ -1133,7 +1133,7 @@ V3Number& V3Number::opShiftR (const V3Number& lhs, const V3Number& rhs) {
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return *this;
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}
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V3Number& V3Number::opShiftRS (const V3Number& lhs, const V3Number& rhs) {
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V3Number& V3Number::opShiftRS (const V3Number& lhs, const V3Number& rhs, uint32_t lbits) {
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// L(lhs) bit return
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// The spec says a unsigned >>> still acts as a normal >>.
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// We presume it is signed; as that's V3Width's job to convert to opShiftR
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@@ -1142,11 +1142,11 @@ V3Number& V3Number::opShiftRS (const V3Number& lhs, const V3Number& rhs) {
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uint32_t rhsval = rhs.toUInt();
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if (rhsval < (uint32_t)lhs.width()) {
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for (int bit=0; bit<this->width(); bit++) {
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setBit(bit,lhs.bitIsExtend(bit + rhsval));
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setBit(bit,lhs.bitIsExtend(bit + rhsval, lbits));
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}
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} else {
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for (int bit=0; bit<this->width(); bit++) {
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setBit(bit,lhs.bitIsExtend(lhs.width()-1));
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setBit(bit,lhs.bitIs(lbits-1));
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}
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}
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return *this;
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@@ -1481,11 +1481,11 @@ V3Number& V3Number::opAssign (const V3Number& lhs) {
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return *this;
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}
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V3Number& V3Number::opExtendS (const V3Number& lhs) {
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V3Number& V3Number::opExtendS (const V3Number& lhs, uint32_t lbits) {
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// Note may be a width change during the sign extension
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setZero();
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for(int bit=0; bit<this->width(); bit++) {
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setBit(bit,lhs.bitIsExtend(bit));
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setBit(bit,lhs.bitIsExtend(bit, lbits));
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}
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return *this;
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}
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