Fix interface data type consistency (#6965) (#7302)

src/V3Param.cpp

@@ -878,10 +878,11 @@ class ParamProcessor final {
                     if (AstTypedef* const newTdp = V3LinkDotIfaceCapture::findTypedefInModule(
                             correctModp, refp->typedefp()->name())) {
                         refp->typedefp(newTdp);
+                        if (newTdp->subDTypep()) refp->refDTypep(newTdp->subDTypep());
                         fixed = true;
                     }
                 }
-                if (refp->refDTypep()) {
+                if (!fixed && refp->refDTypep()) {
                     if (AstNodeDType* const newDtp = V3LinkDotIfaceCapture::findDTypeInModule(
                             correctModp, refp->refDTypep()->name(), refp->refDTypep()->type())) {
                         refp->refDTypep(newDtp);

test_regress/t/t_interface_typedef.py

@@ -13,7 +13,6 @@ test.scenarios('simulator_st')
 
 test.compile(verilator_flags2=['--binary'])
 
-if not test.vlt_all:
+test.execute()
-    test.execute()
 
 test.passes()

test_regress/t/t_interface_typedef.v

@@ -1,18 +1,20 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed under the Creative Commons Public Domain.
+// This program is free software; you can redistribute it and/or modify it
-// SPDX-FileCopyrightText: 2021 Wilson Snyder
+// under the terms of either the GNU Lesser General Public License Version 3
-// SPDX-License-Identifier: CC0-1.0
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 // verilog_format: off
 `define stop $stop
-`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: (%m) %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 // verilog_format: on
 
 interface ifc #(
     parameter int unsigned WIDTH
 ) ();
-  typedef struct {logic [WIDTH-1:0] data;} struct_t;
+  typedef struct packed {logic [WIDTH-1:0] data;} struct_t;
 endinterface
 
 module t (  /*AUTOARG*/
@@ -46,15 +48,15 @@ module sub #(
     input logic clk,
     ifc ifc_if
 );
-  typedef ifc_if.struct_t struct_t;
+  typedef ifc_if.struct_t my_struct_t;
 
   wire [EXP_WIDTH-1:0] expval = '1;
 
   initial begin
-    struct_t substruct;
+    my_struct_t substruct;
     #10;
     substruct.data = '1;
-    `checkh($bits(struct_t), EXP_WIDTH);
+    `checkh($bits(my_struct_t), EXP_WIDTH);
     `checkh(substruct.data, expval);
   end
 

test_regress/t/t_interface_typedef2.py

@@ -4,7 +4,7 @@
 # This program is free software; you can redistribute it and/or modify it
 # under the terms of either the GNU Lesser General Public License Version 3
 # or the Perl Artistic License Version 2.0.
-# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 import vltest_bootstrap
@@ -13,7 +13,6 @@ test.scenarios('simulator_st')
 
 test.compile(verilator_flags2=['--binary'])
 
-if not test.vlt_all:
+test.execute()
-    test.execute()
 
 test.passes()

test_regress/t/t_interface_typedef2.v

@@ -1,8 +1,10 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed under the Creative Commons Public Domain.
+// This program is free software; you can redistribute it and/or modify it
-// SPDX-FileCopyrightText: 2025 Wilson Snyder
+// under the terms of either the GNU Lesser General Public License Version 3
-// SPDX-License-Identifier: CC0-1.0
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 interface common_intf #(
     int ADDR_W,