CDC: Don't report paths to just clocks; resorting senitems in earlier commit messed us up
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@ -207,9 +207,11 @@ private:
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// NODE STATE
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// NODE STATE
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//Entire netlist:
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//Entire netlist:
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// AstVarScope::user1p -> CdcVarVertex* for usage var, 0=not set yet
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// AstVarScope::user1p -> CdcVarVertex* for usage var, 0=not set yet
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// AstVarScope::user2 -> bool Used in sensitivity list
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// {statement}Node::user1p -> CdcLogicVertex* for this statement
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// {statement}Node::user1p -> CdcLogicVertex* for this statement
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// AstNode::user3 -> bool True indicates to print %% (via V3EmitV)
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// AstNode::user3 -> bool True indicates to print %% (via V3EmitV)
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AstUser1InUse m_inuser1;
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AstUser1InUse m_inuser1;
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AstUser2InUse m_inuser2;
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AstUser3InUse m_inuser3;
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AstUser3InUse m_inuser3;
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// STATE
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// STATE
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@ -219,7 +221,7 @@ private:
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AstNodeModule* m_modp; // Current module
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AstNodeModule* m_modp; // Current module
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AstSenTree* m_domainp; // Current sentree
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AstSenTree* m_domainp; // Current sentree
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bool m_inDly; // In delayed assign
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bool m_inDly; // In delayed assign
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int m_senNumber; // Number of senitems
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int m_inSenItem; // Number of senitems
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string m_ofFilename; // Output filename
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string m_ofFilename; // Output filename
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ofstream* m_ofp; // Output file
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ofstream* m_ofp; // Output file
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uint32_t m_userGeneration; // Generation count to avoid slow userClearVertices
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uint32_t m_userGeneration; // Generation count to avoid slow userClearVertices
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@ -237,7 +239,6 @@ private:
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m_logicVertexp->dstDomainp(m_domainp);
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m_logicVertexp->dstDomainp(m_domainp);
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m_logicVertexp->dstDomainSet(true);
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m_logicVertexp->dstDomainSet(true);
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}
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}
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m_senNumber = 0;
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nodep->iterateChildren(*this);
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nodep->iterateChildren(*this);
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m_logicVertexp = NULL;
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m_logicVertexp = NULL;
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@ -266,7 +267,13 @@ private:
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}
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}
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}
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}
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}
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}
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if (m_senNumber > 1) vertexp->cntAsyncRst(vertexp->cntAsyncRst()+1);
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if (m_inSenItem) {
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varscp->user2(true); // It's like a clock...
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// TODO: In the future we could mark it here and do normal clock tree glitch checks also
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} else if (varscp->user2()) { // It was detected in a sensitivity list earlier
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// And now it's used as logic. So must be a reset.
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vertexp->cntAsyncRst(vertexp->cntAsyncRst()+1);
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}
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return vertexp;
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return vertexp;
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}
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}
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@ -591,11 +598,13 @@ private:
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virtual void visit(AstActive* nodep, AstNUser*) {
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virtual void visit(AstActive* nodep, AstNUser*) {
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// Create required blocks and add to module
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// Create required blocks and add to module
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UINFO(4," BLOCK "<<nodep<<endl);
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UINFO(4," BLOCK "<<nodep<<endl);
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AstNode::user2ClearTree();
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m_domainp = nodep->sensesp();
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m_domainp = nodep->sensesp();
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if (!m_domainp || m_domainp->hasCombo() || m_domainp->hasClocked()) { // IE not hasSettle/hasInitial
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if (!m_domainp || m_domainp->hasCombo() || m_domainp->hasClocked()) { // IE not hasSettle/hasInitial
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iterateNewStmt(nodep);
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iterateNewStmt(nodep);
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}
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}
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m_domainp = NULL;
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m_domainp = NULL;
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AstNode::user2ClearTree();
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}
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}
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virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
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virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
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if (m_scopep) {
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if (m_scopep) {
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@ -626,8 +635,9 @@ private:
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virtual void visit(AstSenItem* nodep, AstNUser*) {
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virtual void visit(AstSenItem* nodep, AstNUser*) {
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// Note we look at only AstSenItems, not AstSenGate's
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// Note we look at only AstSenItems, not AstSenGate's
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// The gating term of a AstSenGate is normal logic
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// The gating term of a AstSenGate is normal logic
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m_senNumber++;
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m_inSenItem = true;
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nodep->iterateChildren(*this);
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nodep->iterateChildren(*this);
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m_inSenItem = false;
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}
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}
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virtual void visit(AstAlways* nodep, AstNUser*) {
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virtual void visit(AstAlways* nodep, AstNUser*) {
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iterateNewStmt(nodep);
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iterateNewStmt(nodep);
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@ -690,7 +700,7 @@ public:
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m_modp = NULL;
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m_modp = NULL;
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m_domainp = NULL;
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m_domainp = NULL;
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m_inDly = false;
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m_inDly = false;
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m_senNumber = 0;
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m_inSenItem = 0;
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m_userGeneration = 0;
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m_userGeneration = 0;
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m_filelineWidth = 0;
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m_filelineWidth = 0;
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