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Fix sign extension of pattern members, bug882.

This commit is contained in:
Wilson Snyder 2015-02-12 07:47:45 -05:00
parent 108c0f6bb8
commit 052a7e3deb
3 changed files with 8 additions and 3 deletions
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2
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@ -25,6 +25,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix mis-optimizing gate assignments in unopt blocks, bug881. [Mike Thyer] **** Fix mis-optimizing gate assignments in unopt blocks, bug881. [Mike Thyer]
**** Fix sign extension of pattern members, bug882. [Iztok Jeras]
**** Fix clang compile warnings. **** Fix clang compile warnings.

2
src/V3Width.cpp
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@ -1741,7 +1741,7 @@ private:
if (nodep->lhssp()->nextp()) nodep->v3fatalSrc("PatMember value should be singular w/replicates removed"); if (nodep->lhssp()->nextp()) nodep->v3fatalSrc("PatMember value should be singular w/replicates removed");
// Need to propagate assignment type downwards, even on prelim // Need to propagate assignment type downwards, even on prelim
nodep->iterateChildren(*this,WidthVP(nodep->dtypep(),BOTH).p()); nodep->iterateChildren(*this,WidthVP(nodep->dtypep(),BOTH).p());
iterateCheck(nodep,"Pattern value",nodep->lhssp(),CONTEXT,FINAL,vdtypep,EXTEND_EXP); iterateCheck(nodep,"Pattern value",nodep->lhssp(),CONTEXT,FINAL,vdtypep,EXTEND_LHS);
} }
int visitPatMemberRep(AstPatMember* nodep) { int visitPatMemberRep(AstPatMember* nodep) {
uint32_t times = 1; uint32_t times = 1;

7
test_regress/t/t_math_signed6.v
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@ -3,9 +3,9 @@
// This file ONLY is placed into the Public Domain, for any use, // This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Iztok Jeras. // without warranty, 2015 by Iztok Jeras.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/); module t (/*AUTOARG*/);
// signed source // signed source
logic signed [8-1:0] src; logic signed [8-1:0] src;
@ -17,13 +17,16 @@ module t (/*AUTOARG*/);
} dst; } dst;
initial begin initial begin
// bug882
// verilator lint_off WIDTH // verilator lint_off WIDTH
src = 8'sh05; src = 8'sh05;
dst = '{s: src, u: src}; dst = '{s: src, u: src};
`checkh (dst.s, 16'h0005);
`checkh (dst.u, 16'h0005); `checkh (dst.u, 16'h0005);
src = 8'shf5; src = 8'shf5;
dst = '{s: src, u: src}; dst = '{s: src, u: src};
`checkh (dst.s, 16'hfff5);
`checkh (dst.u, 16'hfff5); `checkh (dst.u, 16'hfff5);
// verilator lint_on WIDTH // verilator lint_on WIDTH