Tests: Add t_sys_file_scan_delay (#4811)

test_regress/t/t_sys_file_scan_delay.dat

@@ -0,0 +1,4 @@
+00000010
+00000011
+
+00000012

test_regress/t/t_sys_file_scan_delay.py

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+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_sys_file_scan_delay.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2024 by David Harris.
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+// verilog_format: on
+
+module t;
+
+  int fd, code;
+  string line;
+  int siglines;
+
+  localparam SIGNATURESIZE = 5000000;
+  logic [31:0] sig32[0:SIGNATURESIZE];
+  logic [31:0] parsed;
+  string signame;
+
+  initial begin
+    signame = "t/t_sys_file_scan_delay.dat";
+
+    fd = $fopen(signame, "r");
+    siglines = 0;
+    if (fd == 0) $display("Unable to read %s", signame);
+    else begin
+      $display("Read %s", signame);
+      while (!$feof(
+          fd
+      )) begin
+        code = $fgets(line, fd);
+        if (code != 0) begin
+          if (line.len() > 1) begin
+            if ($sscanf(line, "%x", sig32[siglines]) != 0) begin
+              $display("sig32[%1d] = %x   line: ", siglines, sig32[siglines], line);
+              siglines = siglines + 1;  // increment if line is not blank
+            end
+          end
+        end
+      end
+      $fclose(fd);
+    end
+
+    `checkh(sig32[0], 32'h10);
+    `checkh(sig32[1], 32'h11);
+    `checkh(sig32[2], 32'h12);
+    $display("*-* All Finished *-*");
+    $finish;
+  end
+
+endmodule