Fix name collision on task inputs, bug569.

Changes

@@ -17,6 +17,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix name collision on unnamed blocks, bug567.  [Chandan Egbert]
 
+****  Fix name collision on task inputs, bug569.  [Chandan Egbert]
+
 
 * Verilator 3.841 2012/09/03
 

src/V3LinkDot.cpp

@@ -1365,6 +1365,7 @@ private:
 	    VSymEnt* okSymp;
 	    VSymEnt* dotSymp = m_curSymp;  // Start search at current scope
 	    if (nodep->inlinedDots()!="") {  // Correct for current scope
+		dotSymp = m_modSymp; // Dotted lookup is always relative to module, as maybe variable name lower down with same scope name we want to ignore (t_math_divw)
 		string inl = AstNode::dedotName(nodep->inlinedDots());
 		dotSymp = m_statep->findDotted(dotSymp, inl, baddot, okSymp);
 		if (!dotSymp) {

src/V3SymTable.h

@@ -60,7 +60,7 @@ private:
 	return level;
     }
 #else
-    static int debug() { return 0; }  // NOT runtime, too hot of a function
+    static inline int debug() { return 0; }  // NOT runtime, too hot of a function
 #endif
 public:
     void dumpIterate(ostream& os, VSymMap& doneSymsr, const string& indent, int numLevels, const string& searchName) {

test_regress/t/t_func_v.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_func_v.v

@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Chandan Egbert.
+
+// See bug569
+
+module t();
+`ifdef T_FUNC_V_NOINL
+   // verilator no_inline_module
+`endif
+   level1 ul1();
+   initial ul1.doit(4'b0);
+endmodule
+
+module level1();
+`ifdef T_FUNC_V_NOINL
+   // verilator no_inline_module
+`endif
+   level2 ul2();
+
+   task doit(input logic [3:0] v);
+      ul2.mem = v;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   endtask
+endmodule
+
+module level2();
+`ifdef T_FUNC_V_NOINL
+   // verilator no_inline_module
+`endif
+   logic [3:0] mem;
+endmodule

test_regress/t/t_func_v_noinl.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_func_v.v");
+
+compile (
+    v_flags2 => ['+define+T_FUNC_V_NOINL',],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;