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Make incorrect soft ordering constraint into a hard constraint. (#5520)
An ordering constraint between NBA commit blocks ('Post' logic) and the
written variable were previously added as soft constraints (cutable
edges). However these are required for correctness, so if it ever is
cut we will have incorrect simulation results.
Change these into hard constraints instead. This necessitates adding a
flag on AstVar to ignore special variables constructed during V3Delayed
that might otherwise appear as degenerate logic loops. E.g.:
if (VdlySet) {
VdlySet = 0; // <- This write to VdlySet can and must be ignored
LHS = VdlyVal;
}
No functional change, but you might get an error if this constraint was
ever violated. (Theoretically it should never be, as these variables
were inserted in a way that does not require violating these constraints
...)
This commit is contained in:
+3
-1
@@ -510,6 +510,7 @@ class DelayedVisitor final : public VNVisitor {
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// Create new flag
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AstVarScope* const flagVscp = createTemp(flp, scopep, "__VdlySet" + baseName, 1);
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flagVscp->varp()->setIgnorePostWrite();
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// Set the flag at the original NBA
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nodep->addHereThisAsNext( //
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new AstAssign{flp, new AstVarRef{flp, flagVscp, VAccess::WRITE},
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@@ -543,6 +544,7 @@ class DelayedVisitor final : public VNVisitor {
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const std::string name = "__VdlyCommitQueue" + vscp->varp()->shortName();
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AstVarScope* const queueVscp = createTemp(flp, scopep, name, cqDTypep);
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queueVscp->varp()->noReset(true);
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queueVscp->varp()->setIgnorePostWrite();
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vscpInfo.valueQueueKit().vscp = queueVscp;
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// Create the AstActive for the Post logic
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AstActive* const activep
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@@ -556,7 +558,7 @@ class DelayedVisitor final : public VNVisitor {
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AstCMethodHard* const callp
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= new AstCMethodHard{flp, new AstVarRef{flp, queueVscp, VAccess::READWRITE}, "commit"};
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callp->dtypeSetVoid();
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callp->addPinsp(new AstVarRef{flp, vscp, VAccess::READWRITE});
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callp->addPinsp(new AstVarRef{flp, vscp, VAccess::WRITE});
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postp->addStmtsp(callp->makeStmt());
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}
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