Add t_split_var_1_bad.{v,pl} for warning test.

test_regress/t/t_split_var_0.v

@@ -2,19 +2,19 @@ module barshift #(parameter depth = 2, localparam width = 2**depth) (
     input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
 
 // If the following split_array var is removed, ALWCOMBORDER and UNOPTFLAT appear.
-logic [width-1:0] tmp[0:depth]; /*verilator split_var*/
+logic [width-1:0] tmp[depth-2:-2]; /*verilator split_var*/
 generate
     for(genvar i = 0; i < depth; ++i) begin
         always_comb
         if (shift[i]) begin
-            tmp[i+1] = {tmp[i][(1 << i)-1:0], tmp[i][width-1:(2**i)]};
+            tmp[i+1-2] = {tmp[i-2][(1 << i)-1:0], tmp[i-2][width-1:(2**i)]};
         end else begin
-            tmp[i + 1] = tmp[i];
+            tmp[i + 1 - 2] = tmp[i-2];
         end
     end
 endgenerate
-assign tmp[0] = in;
-assign out = tmp[depth];
+assign tmp[0-2] = in;
+assign out = tmp[depth-2];
 endmodule
 
 
@@ -36,9 +36,13 @@ logic [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/
 barshift #(.depth(depth)) shifter0(.in(in), .out(out0), .shift(shift));
 
 assign in = 8'b10001110;
+logic [7:0] [7:0] exp = {
+    8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001,
+    8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101};
 always @(posedge clk) begin
-    $display("in:%b shift:%d out:%b", in, shift, out0);
-    if (&shift) begin
+    $display("in:%b shift:%d out:%b exp:%b", in, shift, out0, exp[7-shift]);
+    if (out0 != exp[7-shift]) $stop;
+    if (shift == 7) begin
         $write("*-* All Finished *-*\n");
         $finish;
     end

test_regress/t/t_split_var_1_bad.out

@@ -0,0 +1,22 @@
+%Warning-SPLITVAR: t/t_split_var_1_bad.v:4: Stray pragma of split_var is detected.
+                                          : ... In instance t
+  /*verilator split_var*/ 
+  ^~~~~~~~~~~~~~~~~~~~~~~
+                   ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message.
+%Warning-SPLITVAR: t/t_split_var_1_bad.v:7: Pragma split_var is specified on 'should_show_warning0' which type is not supported yet. Only unpacked 1D array is supported by this version.
+                                          : ... In instance t
+logic should_show_warning0;                /*verilator split_var*/ 
+                                           ^~~~~~~~~~~~~~~~~~~~~~~
+%Warning-SPLITVAR: t/t_split_var_1_bad.v:8: Pragma split_var is specified on 'should_show_warning1' which type is not supported yet. Only unpacked 1D array is supported by this version.
+                                          : ... In instance t
+logic [1:0][7:0]should_show_warning1;      /*verilator split_var*/ 
+                                           ^~~~~~~~~~~~~~~~~~~~~~~
+%Warning-SPLITVAR: t/t_split_var_1_bad.v:9: Pragma split_var is specified on 'should_show_warning2' which type is not supported yet. Only unpacked 1D array is supported by this version.
+                                          : ... In instance t
+wire  [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/ 
+                                           ^~~~~~~~~~~~~~~~~~~~~~~
+%Warning-SPLITVAR: t/t_split_var_1_bad.v:30: Variable "cannot_split" will not be split because index cannot be determined statically.
+                                           : ... In instance t.i_sub0
+    rd_data = cannot_split[addr];
+                           ^~~~
+%Error: Exiting due to

test_regress/t/t_split_var_1_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+);
+
+ok(1);
+1;

test_regress/t/t_split_var_1_bad.v

@@ -0,0 +1,32 @@
+
+
+module t();
+/*stray pragma */ /*verilator split_var*/
+
+// The following variables can not be splitted. will see warnings.
+logic should_show_warning0;                /*verilator split_var*/
+logic [1:0][7:0]should_show_warning1;      /*verilator split_var*/
+wire  [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/
+
+logic [3:0] addr;
+logic [7:0] rd_data;
+
+sub0 i_sub0(.addr(addr), .rd_data(rd_data));
+
+
+initial begin
+    addr = 0;
+    addr = 1;
+    $finish;
+end
+
+endmodule
+
+
+module sub0(input [3:0]addr, output logic [7:0] rd_data);
+
+logic [7:0] cannot_split[0:15];  /*verilator split_var*/
+always_comb
+    rd_data = cannot_split[addr];
+
+endmodule