Add V3Number rotate functions; unused as yet

bin/verilator

@@ -617,7 +617,7 @@ appropriate `begin_keywords.
 
 Specify the extensions that should be used for finding modules.  If for
 example module I<x> is referenced, look in I<x>.I<ext>.  Note +libext+ is
-fairly standard across Verilog tools.
+fairly standard across Verilog tools.  Defaults to .v and .sv.
 
 =item --lint-only
 

src/V3Inline.cpp

@@ -184,7 +184,7 @@ private:
 		// user2p is either a const or a var.
 		AstConst*  exprconstp  = nodep->user2p()->castNode()->castConst();
 		AstVarRef* exprvarrefp = nodep->user2p()->castNode()->castVarRef();
-		UINFO(1,"connectto: "<<nodep->user2p()->castNode()<<endl);
+		UINFO(8,"connectto: "<<nodep->user2p()->castNode()<<endl);
 		if (!exprconstp && !exprvarrefp) {
 		    nodep->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up\n");
 		}

src/V3Number.cpp

@@ -1011,6 +1011,30 @@ V3Number& V3Number::opLteS (const V3Number& lhs, const V3Number& rhs) {
     return opGteS(rhs,lhs);
 }
 
+V3Number& V3Number::opRotR (const V3Number& lhs, const V3Number& rhs) {
+    // L(lhs) bit return
+    if (rhs.isFourState()) return setAllBitsX();
+    setZero();
+    uint32_t rhsval = rhs.toUInt();
+    for (int bit=0; bit<this->width(); bit++) {
+	setBit(bit,lhs.bitIs((bit + rhsval) % this->width()));
+    }
+    return *this;
+}
+
+V3Number& V3Number::opRotL (const V3Number& lhs, const V3Number& rhs) {
+    // L(lhs) bit return
+    if (rhs.isFourState()) return setAllBitsX();
+    setZero();
+    uint32_t rhsval = rhs.toUInt();
+    for (int bit=0; bit<this->width(); bit++) {
+	if (bit >= (int)rhsval) {
+	    setBit(bit,lhs.bitIs((bit - rhsval) % this->width()));
+	}
+    }
+    return *this;
+}
+
 V3Number& V3Number::opShiftR (const V3Number& lhs, const V3Number& rhs) {
     // L(lhs) bit return
     if (rhs.isFourState()) return setAllBitsX();
@@ -1038,8 +1062,8 @@ V3Number& V3Number::opShiftRS (const V3Number& lhs, const V3Number& rhs) {
 V3Number& V3Number::opShiftL (const V3Number& lhs, const V3Number& rhs) {
     // L(lhs) bit return
     if (rhs.isFourState()) return setAllBitsX();
-    uint32_t rhsval = rhs.toUInt();
     setZero();
+    uint32_t rhsval = rhs.toUInt();
     for (int bit=0; bit<this->width(); bit++) {
 	if (bit >= (int)rhsval) {
 	    setBit(bit,lhs.bitIs(bit - rhsval));
@@ -1051,6 +1075,15 @@ V3Number& V3Number::opShiftL (const V3Number& lhs, const V3Number& rhs) {
 //======================================================================
 // Ops - Arithmetic
 
+V3Number& V3Number::opAbsS (const V3Number& lhs) {
+    // op i, L(lhs) bit return
+    if (lhs.isFourState()) return setAllBitsX();
+    if (lhs.isNegative()) {
+	return opUnaryMin(lhs);
+    } else {
+	return opAssign(lhs);
+    }
+}
 V3Number& V3Number::opUnaryMin (const V3Number& lhs) {
     // op i, L(lhs) bit return
     if (lhs.isFourState()) return setAllBitsX();

src/V3Number.h

@@ -202,6 +202,7 @@ public:
     V3Number& opLogNot	(const V3Number& lhs);
     V3Number& opLogAnd	(const V3Number& lhs, const V3Number& rhs);
     V3Number& opLogOr	(const V3Number& lhs, const V3Number& rhs);
+    V3Number& opAbsS    (const V3Number& lhs);
     V3Number& opUnaryMin(const V3Number& lhs);
     V3Number& opAdd	(const V3Number& lhs, const V3Number& rhs);
     V3Number& opSub	(const V3Number& lhs, const V3Number& rhs);
@@ -218,6 +219,8 @@ public:
     V3Number& opXor	(const V3Number& lhs, const V3Number& rhs);
     V3Number& opXnor	(const V3Number& lhs, const V3Number& rhs);
     V3Number& opOr	(const V3Number& lhs, const V3Number& rhs);
+    V3Number& opRotR	(const V3Number& lhs, const V3Number& rhs);
+    V3Number& opRotL	(const V3Number& lhs, const V3Number& rhs);
     V3Number& opShiftR	(const V3Number& lhs, const V3Number& rhs);
     V3Number& opShiftRS	(const V3Number& lhs, const V3Number& rhs); // Arithmetic w/carry
     V3Number& opShiftL	(const V3Number& lhs, const V3Number& rhs);