Add test

Signed-off-by: Pawel Kojma <pkojma@internships.antmicro.com>

test_regress/t/t_clang_overload.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=['--binary', '--timing', '--compiler', 'clang', '-Wno-fatal'])
+
+test.passes()

test_regress/t/t_clang_overload.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+interface irq_if (
+    input logic clk,
+    input logic resetn
+);
+  logic irq;
+  logic te;
+  logic halted;
+  logic fault;
+  logic wfi;
+  clocking cb @(posedge clk);
+    default input #1step output #2ns;
+    output irq;
+    output te;
+    input halted;
+    input fault;
+    input wfi;
+  endclocking
+  modport DUT_IRQ_PORT(input clk, resetn, output halted, fault, wfi);
+endinterface
+class base_test_class;
+  function int foo();
+  endfunction
+  virtual irq_if.DUT_IRQ_PORT irq_vif;
+  function new(string name);
+  endfunction
+  virtual function void build_phase();
+    if (irq_vif == null) begin
+      if (foo()) $display();
+    end
+  endfunction
+endclass
+module tb_top;
+endmodule