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Fix bit reductions on multi-packed dimensions, bug227/patch0004.

This commit is contained in:
Wilson Snyder 2010-04-22 09:40:53 -04:00
parent aca4ab015f
commit 00970be996
3 changed files with 31 additions and 3 deletions
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4
Changes
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@ -11,11 +11,11 @@ indicates the contributor was also the author of the fix; Thanks!
*** Fix word size to match uint64_t on -m64 systems, bug238. [Joe Eiler]
**** Improve error handling on slices of arrays, bug226. [by Bryon Bradley]
**** Improve error handling on slices of arrays, bug226. [by Byron Bradley]
**** Report errors when extra underscores used in meta-comments.
**** Fix bit reductions on multi-packed dimensions, bug227. [by Bryon Bradley]
**** Fix bit reductions on multi-packed dimensions, bug227. [by Byron Bradley]
**** Fix removing $fscanf if assigned to unused var, bug248. [Ashutosh Das]

19
src/V3Slice.cpp
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@ -134,7 +134,8 @@ class SliceCloneVisitor : public AstNVisitor {
nodep->unlinkFrBack()->deleteTree(); nodep = NULL;
}
virtual void visit(AstNodeUniop* nodep, AstNUser*) {
// Not all Uniop nodes should be cloned down to a single bit
void cloneUniop(AstNodeUniop* nodep) {
if (nodep->user2() < 2) return; // Don't need clones
m_selBits.clear();
UINFO(4, "Cloning "<<nodep->user2()<<" times: "<<nodep<<endl);
@ -181,6 +182,22 @@ class SliceCloneVisitor : public AstNVisitor {
nodep->unlinkFrBack()->deleteTree(); nodep = NULL;
}
virtual void visit(AstRedOr* nodep, AstNUser*) {
cloneUniop(nodep);
}
virtual void visit(AstRedAnd* nodep, AstNUser*) {
cloneUniop(nodep);
}
virtual void visit(AstRedXor* nodep, AstNUser*) {
cloneUniop(nodep);
}
virtual void visit(AstRedXnor* nodep, AstNUser*) {
cloneUniop(nodep);
}
virtual void visit(AstNode* nodep, AstNUser*) {
// Default: Just iterate
nodep->iterateChildren(*this);

11
test_regress/t/t_mem_packed.v
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@ -116,6 +116,12 @@ module t (/*AUTOARG*/
assign vld_and = &vld[0][0];
assign vld2_and = &vld2;
// Bit reductions should be cloned, other unary operations should clone the
// entire assign.
logic [3:0][7:0][1:0] not_lhs;
logic [3:0][7:0][1:0] not_rhs;
assign not_lhs = ~not_rhs;
// Test an AstNodeUniop that shouldn't be expanded
logic [3:0][7:0][1:0] vld2_inv;
assign vld2_inv = ~vld2;
@ -127,10 +133,13 @@ module t (/*AUTOARG*/
vld[0][0][i+1][j+1] = 2'b00;
vld2[i][j] = 2'b00;
vld2[i+1][j+1] = 2'b00;
not_rhs[i][j] = i[1:0];
not_rhs[i+1][j+1] = i[1:0];
end
end
end
logic [3:0] expect_cyc; initial expect_cyc = 'd15;
always @(posedge clk) begin
@ -139,6 +148,8 @@ module t (/*AUTOARG*/
for (int j=0; j<8; j=j+1) begin
vld[0][0][i][j] <= vld[0][0][i][j] + 1;
vld2[i][j] <= vld2[i][j] + 1;
if (not_rhs[i][j] != ~not_lhs[i][j]) $stop;
not_rhs[i][j] <= not_rhs[i][j] + 1;
end
end
if (cyc % 8 == 0) begin